Dual boot panel SWAP mechanism

Patent metadata

Field	Value
Publication number	US-9858083-B2
Application number	US-201414204208-A
Country	US
Kind code	B2
Filing date	Mar 11, 2014
Priority date	Mar 14, 2013
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A central processing unit with dual boot capabilities is disclosed comprising an instruction memory further comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively. The instruction set for the central processing unit comprises a dedicated instruction that allows to perform a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the dedicated instruction in the active memory followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

First claim

What is claimed is:

1. A central processing unit with dual boot capabilities, comprising:
an instruction memory comprising a first and second memory area which are configured to be individually programmable, wherein first and second memory area can be assigned to an active memory from which instructions are executed and an inactive memory, respectively;
wherein the instruction set for the central processing unit comprises a opcode, the sole purpose of the opcode to cause a swap from the an active memory area to an inactive memory area, wherein the swap is performed by executing the opcode in the active memory immediately followed by a program flow change instruction in the active memory, whereupon the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

2. The central processing unit according to claim 1 , wherein the program flow change instruction is a branch or jump instruction.

3. The central processing unit according to claim 1 , further comprising a control register comprising at least one status bit which is set when said opcode has been successfully executed.

4. The central processing unit according to claim 3 , wherein the opcode acts as a no operation instruction when a swap cannot be successfully performed, wherein the no operation instruction advances a program counter to skip the program flow change instruction.

5. The central processing unit according to claim 1 , further comprising a control register comprising at least one control bit which must be set to allow a swap from the active memory to the inactive memory.

6. The central processing unit according to claim 5 , wherein the at least one control bit is set by setting said control bit at least twice within a predetermined time window.

7. The central processing unit according to claim 6 , wherein the time window is 2 instruction cycles.

8. The central processing unit according to claim 1 , wherein the inactive memory is configured to be programmable while a program is executed from the active memory.

9. The central processing unit according to claim 1 , wherein during initialization, the central processing unit is configured to assign the first memory area to the active memory based at least in part on a panel select value read from nonvolatile memory.

10. The central processing unit according to claim 9 , wherein the panel select value in nonvolatile memory is modified as a result of successful execution of the opcode.

11. The central processing unit according to claim 9 , wherein the panel select value in nonvolatile memory is modifiable by a software instruction subsequent to successful execution of the opcode.

12. The central processing unit according to claim 1 , further comprising a control register configured to enable or disable said opcode.

13. The central processing unit according to claim 12 , wherein to allow execution of the opcode the control register must be written with a first value followed by a second value within a predetermined time window, wherein the second value is a digital value inverse to the first value.

14. The central processing unit according to claim 13 , wherein the time window is 2 instruction cycles.

15. The central processing unit according to claim 3 , further comprising the step of enabling said opcode to be executable only after said at least one status bit in the control register has been cleared.

16. The central processing unit according to claim 15 , wherein said at least one status bit in the control register cannot be set by an instruction.

17. A method of operating a central processing unit with dual boot capabilities, comprising:
providing an instruction memory with a first and second memory area which are configured to be individually programmable;
assigning the first memory area to be an active memory from which instructions are executed and the second memory are to an inactive memory, wherein the central processing unit comprises an instruction set that includes a opcode, the sole purpose of the opcode when executed is to cause a swap from the first memory area to the second memory area, wherein the opcode is configurable to be executable or not executable;
configuring the opcode to be executable;
executing the opcode in the active memory followed by a program flow change instruction in the active memory, whereupon execution of the instructions the inactive memory becomes the new active memory and the active memory becomes the new inactive memory and execution of instructions continues in the new active memory.

18. The method according to claim 17 , wherein the program flow change instruction is a branch or jump instruction.

19. The method according to claim 17 , further comprising the step of automatically setting at least one status bit in a control register when said opcode has been successfully executed.

20. The method according to claim 19 , further comprising the step of enabling said opcode to be executable only after said at least one status bit in the control register has been cleared.

21. The method according to claim 20 , wherein said at least one status bit in the control register cannot be set by an instruction.

22. The method according to claim 20 , wherein the opcode acts as a no operation instruction when the opcode is not enabled, wherein the no operation instruction advances a program counter to skip the program flow change instruction.

23. The method according to claim 17 , further comprising the step of setting a control bit in a control register before executing the opcode wherein setting the control bit enables execution of the opcode.

24. The method according to claim 23 , further comprising setting the at least one control bit at least twice within a predetermined time window before executing the opcode whereupon execution of the opcode is enabled.

25. The method according to claim 24 , wherein the predetermined time window is 2 instruction cycles long.

26. The method according to claim 17 , further comprising the step of programming the inactive memory while a program is executed from the active memory.

27. The method according to claim 17 , wherein during initialization, the central processing unit assigns the first memory area to the active memory based at least in part on a panel select value read from nonvolatile memory.

28. The method according to claim 27 , wherein the panel select value in nonvolatile memory is modified as a result of successful execution of the opcode.

29. The method according to claim 27 , wherein the panel select value in nonvolatile memory is modifiable by a software instruction subsequent to successful execution of the opcode.

30. The method according to claim 17 , further comprising the step of writing a first value to a control register and subsequently writing a second value to the control register within a predetermined time window to enable said opcode, wherein the second value is a digital value inverse to the first value.

31. The method according to claim 30 , wherein the time window is 2 instruction cycles.

32. A central processing unit with dual boot capabilities, comprising:
an instruction memory comprising a first and second memory area which are configured to be individually programmable, whe

Assignees

• Microchip Tech Inc

Inventors

• Catherwood Michael I
• Ivey Brant
• Wojewoda Igor
• Mickey David
• Kanellopoulos Joseph

Classifications

• G06F9/441 Primary

  Multiboot arrangements, i.e. selecting an operating system to be loaded · CPC title

• G06F9/4401 Primary

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F8/67

  Physics · mapped topic

• G06F8/656

  while running · CPC title