Electronic system with update control mechanism and method of operation thereof

Patent metadata

Field	Value
Publication number	US-9858067-B2
Application number	US-201615067887-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Oct 5, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

An electronic system includes: an interface control unit to receive a write buffer command; a command core executes a firmware update based on the write buffer command; a non-volatile memory array configured to store an image of a primary file system, a secondary file system, a primary firmware, and a secondary firmware; a TCM configured to contain an operating firmware; and a volatile memory configured to store the write buffer command including a product image; wherein: the command core executes in order: verify the product image, extract an operating firmware executable and a SSFS update from the product image, copy the operating firmware executable to the secondary firmware, restart the operating firmware with the operating firmware executable copied to the TCM, copy the SSFS update to the secondary file system, copy the operating firmware executable to the primary firmware, and copy the SSFS update to the primary file system.

First claim

What is claimed is:

1. A electronic system comprising:
an interface control unit configured to receive a write buffer command;
a command core, coupled to the interface control unit, configured to execute a firmware update based on the write buffer command;
a non-volatile memory array, coupled to the command core, configured to store an image of a primary file system, a secondary file system, a primary firmware, and a secondary firmware;
a tightly coupled memory (TCM), coupled to the command core, configured to contain an operating firmware; and
a volatile memory, coupled to the interface control unit, configured to store the write buffer command including a product image;
wherein:
the command core is configured to execute in order:
verify the product image,
extract an operating firmware executable and a solid state file system (SSFS) update from the product image,
copy the operating firmware executable to the secondary firmware,
restart the operating firmware with the operating firmware executable copied to the TCM,
copy the SSFS update to the secondary file system,
copy the operating firmware executable to the primary firmware, and
copy the SSFS update to the primary file system.

2. The system as claimed in claim 1 wherein the command core is a portion of a device processor configured to control the firmware update.

3. The system as claimed in claim 1 further comprising a boot read-only memory (ROM), coupled to the command core, configured to: copy the primary firmware to the TCM; verify the primary file system is compatible with the primary firmware; and repair the primary file system, by copying the secondary file system to the primary file system, when the primary firmware is incompatible.

4. The system as claimed in claim 1 wherein the interface control unit includes a maskable reset coupled to and disabled by the command core.

5. The system as claimed in claim 1 further comprising a TCM reserved, coupled to the command core, loaded with a programming logic from the product image.

6. The system as claimed in claim 1 wherein the non-volatile memory array is configured to include a system area, containing the primary firmware and the secondary firmware, and a solid state file system, containing the primary file system and the secondary file system.

7. The system as claimed in claim 1 wherein the volatile memory configured to store the write buffer command includes the write buffer command starting at a fixed address of a host command queue.

8. The system as claimed in claim 1 wherein the command core is one of multiple processor cores, in a device processor, configured to idle the remaining of the multiple processor cores during the firmware update.

9. The system as claimed in claim 1 wherein the interface controller is configured to verify the write buffer command by performing an on-the-fly circular redundancy check (CRC) including the write buffer command CRC value.

10. The system as claimed in claim 1 wherein the command core can be any of the multiple processor cores in a device processor.

11. A method of operation of an electronic system, the system comprising:
an interface control unit configured to receive a write buffer command;
a command core, coupled to the interface control unit, configured to execute a firmware update based on the write buffer command;
a non-volatile memory array, coupled to the command core, configured to store an image of a primary file system, a secondary file system, a primary firmware, and a secondary firmware; a tightly coupled memory (TCM), coupled to the command core, configured to contain an operating firmware; and
a volatile memory, coupled to the interface control unit, configured to store the write buffer command including a product image;
the method comprising:
receiving a write buffer command; and
executing a firmware update based on the write buffer command including executing in order:
verifying the product image in the write buffer command,
extracting an operating firmware executable and a solid state file system (SSFS) update from the product image,
copying the operating firmware executable to the secondary firmware, restarting the operating firmware with the operating firmware executable copied to the TCM, copying the SSFS update to the secondary file system,
copying the operating firmware executable to the primary firmware, and
copying the SSFS update to the primary file system.

12. The method as claimed in claim 11 wherein executing the firmware update includes selecting the command core as a portion of a device processor.

13. The method as claimed in claim 11 further comprising:
copying the primary firmware to the TCM;
verifying the primary file system is compatible with the primary firmware; and
repairing the primary file system, by copying the secondary file system to the primary file system, when the primary firmware is incompatible.

14. The method as claimed in claim 11 further comprising disabling a maskable reset coupled to the command core.

15. The method as claimed in claim 11 further comprising loading a TCM reserved with a programming logic from the product image.

16. The method as claimed in claim 11 further comprising configuring the non-volatile memory array to include a system area, containing the primary firmware and the secondary firmware, and a solid state file system, containing the primary file system and the secondary file system.

17. The method as claimed in claim 11 further comprising configuring the volatile memory to store the write buffer command includes starting the write buffer command at a fixed address of a host command queue.

18. The method as claimed in claim 11 further comprising idling, by the command core, the remaining of the multiple processor cores during the firmware update.

19. The method as claimed in claim 11 further comprising verifying the write buffer command by performing an on-the-fly circular redundancy check (CRC) including the write buffer command CRC value.

20. The method as claimed in claim 11 further comprising selecting the command core by the first available of the multiple processor cores in a device processor.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ozturk Ayberk
• Deglin Richard

Classifications

• G06F8/654 Primary

  using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title

• G06F8/65

  Updates (security arrangements therefor G06F21/57) · CPC title

• G06F8/665 Primary

  Physics · mapped topic