Error cancellation in a current digital-to-analog converter of a continuous-time sigma-delta modulator

Patent metadata

Field	Value
Publication number	US-9853653-B2
Application number	US-201615259292-A
Country	US
Kind code	B2
Filing date	Sep 8, 2016
Priority date	Sep 15, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Apparatus and methods for reducing noise and distortion in current digital-to-analog converters (IDACs). Compensating capacitors may be connected to current sources in an IDAC. The compensating capacitors may be driven with signals 5 derived from the output of the IDAC to cancel transient current spikes that would otherwise occur on the output of the IDAC.

First claim

What is claimed is:

1. A current digital-to-analog converter (IDAC) comprising:
a first current source arranged to provide current to a first output and/or a second current source arranged to pull current from the first output;
a first compensating capacitor connected to the first current source and/or a second compensating capacitor connected to the second current source; and
driving circuitry configured to supply current to the first compensating capacitor and/or the second compensating capacitor.

2. The IDAC of claim 1 , wherein the first compensating capacitor and the second compensating capacitor are arranged to compensate for associated capacitances of the first current source and the second current source.

3. The IDAC of claim 1 , further comprising a first switch and a second switch arranged to intermittently conduct current to and from the first output.

4. The IDAC of claim 3 , wherein the driving circuity is configured to be switched to receive and amplify, with an amplifier, a signal from the first output with a same signal that controls the first switch.

5. The IDAC of claim 4 , connected in a sigma-delta modulator, wherein the sigma-delta modulator has a sampling frequency and an operating bandwidth of the amplifier is approximately equal to or greater than the sampling frequency.

6. The IDAC of claim 1 , wherein the driving circuitry comprises an amplifier having a gain between approximately 1.5 and approximately 2.7.

7. The IDAC of claim 6 , wherein the amplifier comprises:
a first input connected to a reference voltage; and
a second input connected to switches that are arranged to connect the second input to either the first output of the IDAC or a second output of the IDAC.

8. The IDAC of claim 6 , wherein the amplifier has an operating bandwidth between approximately 2 GHz and approximately 4 GHz.

9. The IDAC of claim 1 , further comprising:
a second output; and
a third switch and a fourth switch arranged to conduct current intermittently to and from the second output.

10. The IDAC of claim 9 , wherein the first switch and the fourth switch are configured to be controlled by a same signal, and the second switch and the third switch are configured to be controlled by a same signal.

11. The IDAC of claim 9 , wherein the driving circuitry includes an amplifier that comprises:
a first input connected to a reference voltage; and
a second input connected to switches that are arranged to connect the second input to either the first output of the IDAC or the second output of the IDAC.

12. The IDAC of claim 11 , wherein the second input of the amplifier connects to a fifth switch that is configured to be controlled by a same signal that controls the first switch and the fourth switch, and wherein the second input of the amplifier connects to a sixth switch that is configured to be controlled by a same signal that controls the second switch and the third switch.

13. The IDAC of claim 1 , further comprising:
a summing node connected to receive the first output and an input signal for conversion;
an integrator connected to receive an output from the summing node; and
a comparator having an input connected to receive an output of the integrator and an output connected to an input of the IDAC.

14. A current digital-to-analog converter (IDAC) comprising:
a first current source arranged to provide current to or pull current from a first output;
a first compensating capacitor connected to the first current source;
a reference node arranged to connect the first output to a reference potential; and
driving circuitry configured to supply current to the first compensating capacitor.

15. The IDAC of claim 14 , wherein the first compensating capacitor is arranged to compensate for associated capacitance of the first current source.

16. The IDAC of claim 14 , further comprising:
a first switch located between the first current source and the first output; and
a second switch located between the first output and the reference node.

17. The IDAC of claim 16 , wherein the driving circuity is configured to be switched to receive and amplify, with an amplifier, a signal from the first output with a same signal that controls the first switch.

18. The IDAC of claim 17 , connected in a sigma-delta modulator, wherein the sigma-delta modulator has a sampling frequency and an operating bandwidth of the amplifier is approximately equal to or greater than the sampling frequency.

19. The IDAC of claim 14 , wherein the driving circuitry comprises an amplifier having a gain between approximately 1.5 and approximately 2.7.

20. The IDAC of claim 14 , further comprising:
a second output;
a third switch connected between the first current source and the second output; and
a fourth switch connected between the second output and the reference node.

21. A method for converting a digital signal to an analog signal, the method comprising:
driving a first switch connected between a first current source and a first output;
amplifying a first signal from the first output when the first switch is driven to connect the first current source and the first output; and
providing the amplified first signal from the first output to a first compensating capacitor connected to the first current source.

22. The method of claim 21 , further comprising:
driving a second switch connected between the first output and a second current source with a second signal; and
providing an inverse of the amplified first signal from the first output to a second compensating capacitor connected to the second current source.

23. The method of claim 22 , further comprising:
driving a third switch connected between the first current source and a second output with the second signal; and
driving a fourth switch connected between the second output and the second current source with the first signal.

24. The method of claim 23 , further comprising:
amplifying a second signal from the second output when the second switch is driven to connect the second current source and the first output; and
providing the amplified second signal from the second output to the first compensating capacitor and an inverse of the second signal to a second compensating capacitor connected to the second current source.

25. The method of claim 21 , wherein the amplifying comprises amplifying the first signal with a gain between 1.5 and 2.7.

26. The method of claim 21 , further comprising selecting a capacitance of the first compensating capacitor to be essentially equal to an associated capacitance of the first current source that is connected in parallel with the first current source.

27. The method of claim 21 , further comprising providing a signal from the first output to a summing node of a sigma-delta modulator.

Assignees

• Mediatek Inc

Inventors

• Kao Tsung-Kai

Classifications

• H03M1/06 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M1/742

  using current sources as quantisation value generators · CPC title

• H03M3/50 Primary

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• H03M1/0863 Primary

  of switching transients, e.g. glitches · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title