Parallel inverter scheme for separating conduction and switching losses

Patent metadata

Field	Value
Publication number	US-9853570-B2
Application number	US-201615210305-A
Country	US
Kind code	B2
Filing date	Jul 14, 2016
Priority date	Feb 26, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

In one example embodiment, a controller is coupled to a first inverter and a second inverter forming a parallel inverter scheme. The first inverter and the second inverter are configured to provide power to a load. The controller is configured to control the first inverter to operate according to a first operating state, while the second inverter is off, and turn off the first inverter before transition from the first operating state to a second operating state. The controller is further configured to control the second inverter to at least partially operate during the transition.

First claim

What is claimed is:

1. A controller coupled to a first inverter and a second inverter forming a parallel inverter scheme, the first inverter and the second inverter configured to provide power to a load, the controller configured to:
control the first inverter to operate according to a first switching state while the second inverter is off;
turn on the second inverter such that the first inverter and the second inverter simultaneously operate according to the first switching state to share current during a first zero voltage switching (ZVS) period before the first inverter is turned off;
turn off the first inverter after the first ZVS period and before a transition from the first switching state to a second switching state;
control the second inverter to operate during the transition from the first switching state to the second switching state while the first inverter is off;
turn on the first inverter after the transition such that the first inverter and the second inverter simultaneously operate according to the second switching state to share the current during a second ZVS period before the second inverter is turned off;
turn off the second inverter after the second ZVS period; and
control the first inverter to operate according to the second switching state.

2. The controller of claim 1 , wherein
the first inverter includes a first plurality of pairs of switches,
the second inverter includes a second plurality of pairs of switches, and
while controlling the second inverter to operate during the transition, the controller is configured to turn on one or more of the second plurality of pairs of switches of the second inverter corresponding to one or more of the first plurality of pairs of switches of the first inverter that operate differently in the second switching state compared to the first switching state.

3. The controller of claim 1 , wherein
the first inverter is comprised of a first plurality of transistors, and
the second inverter is comprised of a second plurality of transistors.

4. The controller of claim 3 , wherein each of the first plurality of transistors and the second plurality of transistors are power switches.

5. The controller of claim 1 , wherein the controller is configured to supply a first set of voltages to the first inverter and a second set of voltages to the second inverter for controlling the first inverter and the second inverter based on current requirements and feedback from the first inverter and the second inverter.

6. A voltage command generator coupled to a parallel inverter scheme including a first inverter and a second inverter, the voltage command generator configured to,
receive a plurality of voltage commands from a machine controller; and
generate a plurality of control commands based on each of the plurality of voltage commands to,
control the first inverter to operate according to a first switching state while the second inverter is off,
turn on the second inverter such that the first inverter and the second inverter simultaneously operate according to the first switching state to share current during a first zero voltage switching (ZVS) period before the first inverter is turned off,
turn off the first inverter after the first ZVS period and before a transition from the first switching state to a second switching state,
control the second inverter to operate during the transition from the first switching state to the second switching state while the first inverter is off,
turn on the first inverter after the transition such that the first inverter the second inverter simultaneously operate according to the second switching state to share the current during a second ZVS period before the second inverter is turned off,
turn off the second inverter after the second ZVS period, and
control the first inverter to operate according to the second switching state.

7. The voltage command generator of claim 6 , wherein
the first inverter includes a first plurality of pairs of switches,
the second inverter include a second plurality of pairs of switches, and
while controlling the second inverter to operate during the transition, the voltage command generator is configured to generate one or more control commands to turn on one or more of the second plurality of pairs of switches of the second inverter corresponding to one or more of the first plurality of pairs of switches of the first inverter that operate differently in the second switching state compared to the first switching state.

8. The voltage command generator of claim 6 , wherein
the first inverter is comprised of a first plurality of transistors, and
the second inverter is comprised of a second plurality of transistors.

9. The voltage command generator of claim 8 , wherein each of the first plurality of transistors and the second plurality of transistors are power switches.

10. The voltage command generator of claim 6 , wherein the machine controller is configured to provide the plurality of voltage commands according to current requirements and feedback from the first inverter and the second inverter.

11. A parallel inverter scheme comprising:
a first inverter and a second inverter configured to operate according to a plurality of voltage commands received from a machine controller such that,
the first inverter is configured to operate according to a first switching state while the second inverter is off, and
the second inverter is configured to turn on such that the first inverter and the second inverter simultaneously operate according to the first switching state to share current during a first zero voltage switching (ZVS) period before the first inverter is turned off,
the first inverter is configured to turn off after the first ZVS period and before a transition from the first switching state to a second switching state,
the second inverter is configured to operate during the transition from the first switching state to the second switching state while the first inverter is off,
the first inverter is configured to turn on after the transition such that the first inverter and the second inverter simultaneously operate according to the second switching state to share current during a second ZVS period before the second inverter is turned off,
the second inverter is configured to turn off after the second ZVS period, and
the first inverter is configured to operate according to the second switching state.

12. The parallel inverter scheme of claim 11 , wherein
the first inverter includes a first plurality of pairs of switches,
the second inverter include a second plurality of pairs of switches, and
while operating during the transition, the second inverter is configured to turn on one or more of the second plurality of pairs of switches of the second inverter corresponding to one or more of the first plurality of pairs of switches of the first inverter that operate differently in the second switching state compared to the first switching state.

13. The parallel inverter scheme of claim 11 , wherein
the first inverter is comprised of a first plurality of transistors, and
the second inverter is comprised of a second plurality of transistors.

14. The parallel inverter scheme of claim 13 , wherein each of the first plurality of transistors and each of the second plurality of transistors are power switches.

15. The parallel inverter scheme of claim 11 , wherein the machine controller is configured to provide the plurality of voltage commands according to current requirements and feedback from the first inverter and the second inverter.

Assignees

• Deere & Co

Inventors

• Maly Doug

Classifications

• H02P21/06

  Rotor flux based control involving the use of rotor position or rotor speed sensors · CPC title

• B60L3/003

  relating to inverters · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H02P27/08

  with pulse width modulation · CPC title

• H02P27/06

  using DC to AC converters or inverters (H02P27/05 takes precedence) · CPC title