Laminate sub-mounts for LED surface mount package

US9853199B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9853199-B1
Application numberUS-201615042927-A
CountryUS
Kind codeB1
Filing dateFeb 12, 2016
Priority dateOct 3, 2014
Publication dateDec 26, 2017
Grant dateDec 26, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An LED package is described that acts as a sub-mount between a printed circuit board and a diode. The sub-mount includes a laminate to thermally isolate the diode, for example an LED, from the PCB while providing a thermal heat dissipative sink for the diode.

First claim

Opening claim text (preview).

What is claimed is: 1. A diode package comprising: a laminate sub-mount including: a first segmented planar metal layer defining a bottom portion of said sub-mount and having a thickness between 17 microns and 70 microns; a first heat dissipating planar dielectric layer having an uppermost top surface and a lower most bottom surface wherein no substantial portion of said first heat dissipating planar dielectric layer extends above said uppermost top surface of said first heat dissipating planar dielectric layer, said first heat dissipating planar dielectric layer positioned above said first segmented planar metal layer; a second segmented metal layer defining a top portion of said sub-mount, said second segmented metal layer forming at least one conductive pad above said first heat dissipating planar dielectric layer and having a thickness between 17 microns and 1 mm, wherein said first heat dissipating planar dielectric layer isolates said first segmented planar metal layer from said second segmented metal layer; wherein via are formed through said first heat dissipating planar dielectric layer to electrically interconnect said at least one conductive pad with isolated portions of said first segmented planar metal layer; a metal core supporting a diode and having a top segment aligned coplanar with the top portion of said sub-mount and a bottom segment aligned coplanar with the bottom portion of said sub-mount; said diode coupled to the top portion of said sub-mount and electrically coupled to said at least one conductive pad; and a second heat dissipating planar dielectric layer and a third metal layer sandwiched between said second segmented metal layer and said first heat dissipating planar dielectric layer. 2. The diode package as recited in claim 1 , wherein said first heat dissipating planar dielectric layer has a thickness between 10 microns and 200 microns and is made from a ceramic filled polymer. 3. The diode package as recited in claim 1 , wherein said metal core includes a multi-layer metal composite. 4. A diode package comprising: a sub-mount capable of mounting a diode to a circuit board, said sub-mount including: a first metal layer having an uppermost top surface and a lowermost bottom surface, wherein no substantial portion of said first metal layer extends above said uppermost top surface, said bottom surface defining a bottom portion of said sub-mount and said first metal layer having a thickness between 17 microns and 70 microns; a first heat dissipating planar dielectric layer having a thickness between 10 microns and 200 microns and made from a ceramic filled polymer and positioned above said uppermost top surface of said first metal layer; a second metal layer having a thickness between 17 microns and 1 mm and having a top portion that defines a top portion of said sub-mount; a metal core having a top segment aligned coplanar with the top portion of said sub-mount and a bottom segment aligned coplanar with the bottom portion of said sub-mount; a second heat dissipating planar dielectric layer and a third metal layer sandwiched between said second segmented metal layer and said first heat dissipating planar dielectric layer; and wherein said second metal layer is segmented to form at least one conductive pad layered above said first dielectric, and wherein a via is formed through said first planar dielectric layer to electrically interconnect said at least one conductive pad with an electrically isolated portion of said first metal layer. 5. The diode package as recited in claim 4 , further including a light emitting diode electrically coupled to said at least one conductive pads. 6. The diode package as recited in claim 4 , wherein said ceramic filled polymer includes a polymer selected from the group consisting of epoxies, polyimides, cyanate esters, silicones, phenolics, BT resins, benzocyclobutene, silicone, polyphenylsulfone, polyester, and PEN. 7. The diode package as recited in claim 4 , wherein said ceramic filled polymer includes a ceramic filler selected from the group consisting of boron nitride, aluminum oxide, aluminum nitride, silicone carbide, silicon nitride, silica, magnesium oxide, zinc oxide, zirconium oxide, and titanium dioxide. 8. The diode package as recited in claim 4 , wherein said metal core supports said diode. 9. The diode package as recited in claim 8 , wherein said metal core includes an insulating layer sandwiched between said top portion and bottom portion of said sub-mount. 10. The diode package as recited in claim 9 , wherein said metal core is not electrically coupled with said diode and said metal core includes a multi-layer metal composite.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • the connected ends being wedge-shaped · CPC title

  • Die-attach connectors and bond wires · CPC title

  • Electricity · mapped topic

  • H01L33/642Primary

    Electricity · mapped topic

Patent family

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9853199B1 cover?
An LED package is described that acts as a sub-mount between a printed circuit board and a diode. The sub-mount includes a laminate to thermally isolate the diode, for example an LED, from the PCB while providing a thermal heat dissipative sink for the diode.
Who is the assignee on this patent?
Henkel IP & Holding GmbH
What technology area does this patent fall under?
Primary CPC classification H01L33/642. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 26 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).