Method of manufacturing semiconductor device and structure
US-2015364510-A1 · Dec 17, 2015 · US
US9853180B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9853180-B2 |
| Application number | US-201313921756-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 19, 2013 |
| Priority date | Jun 19, 2013 |
| Publication date | Dec 26, 2017 |
| Grant date | Dec 26, 2017 |
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A multijunction solar cell including an upper first solar subcell; a second solar subcell adjacent to the first solar subcell; a first graded interlayer adjacent to the second solar subcell; a third solar subcell adjacent to the first graded interlayer such that the third subcell is lattice mismatched with respect to the second subcell. A second graded interlayer is provided adjacent to the third solar subcell, and a lower fourth solar subcell is provided adjacent to the second graded interlayer, such that the fourth subcell is lattice mismatched with respect to the third subcell. An encapsulating layer composed of silicon nitride or titanium oxide disposed on the top surface of the solar cell, and an antireflection coating layer disposed over the encapsulating layer.
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The invention claimed is: 1. A method of manufacturing a solar cell comprising: providing a first substrate; forming an upper first solar subcell having a first band gap on said first substrate; forming a second solar subcell adjacent to said first solar subcell and having a second band gap smaller than said first band gap; forming a first graded interlayer adjacent to said second solar subcell, said first graded interlayer having a third band gap greater than said second band gap; forming a third solar subcell adjacent to said first graded interlayer, said third subcell having a fourth band gap smaller than said second band gap such that said third subcell is lattice mismatched with respect to said second subcell; forming a second graded interlayer adjacent to said third solar subcell, said second graded interlayer having a fifth band gap greater than said fourth band gap; forming a lower fourth solar subcell adjacent to said second graded interlayer, said lower subcell having a sixth band gap smaller than said fourth band gap such that said fourth subcell is lattice mismatched with respect to said third subcell; mounting a surrogate substrate on top of said fourth solar subcell; removing the first substrate; etching a first trough around the periphery of said solar cell to the surrogate substrate so as to form a mesa structure on said surrogate substrate; passivating an exposed surface of the solar cell with a passivating solution; depositing an encapsulating layer over the passivated surface by chemical vapor deposition immediately after the passivating step; and depositing an anti-reflection coating layer over the encapsulating layer. 2. The method defined in claim 1 , further comprising forming a backside contact layer on the lower fourth solar subcell. 3. The method as defined in claim 2 , further comprising forming discrete, spaced-apart bonding pads over a surface of the backside contact layer. 4. The method as defined in claim 2 , further comprising forming a contact metal layer over the backside contact layer. 5. The method as defined in claim 4 , wherein the depth of the first trough extends down to said contact metal layer. 6. The method as defined in claim 1 , wherein the passivating step is performed by application of ammonium sulphide. 7. The method as defined in claim 1 , wherein the encapsulating layer is composed of silicon nitride or titanium oxide. 8. The method as defined in claim 1 , wherein the passivating step is performed by dipping a wafer in a solution of ammonium sulphide. 9. A method as defined in claim 1 , wherein the lower fourth subcell has a band gap in the range of 0.6 to 0.8 eV; the third subcell has a band gap in the range of 0.9 to 1.1 eV, the second subcell has a band gap in the range of 1.35 to 1.45 eV, and the first subcell has a band gap in the range of 1.8 to 2.1 eV. 10. A method as defined in claim 9 , wherein the first substrate is composed of gallium arsenide or germanium, and the surrogate substrate is composed of sapphire, GaAs, Ge or Si. 11. A method as defined in claim 9 , wherein the first graded interlayer is compositionally graded to lattice match the second subcell on one side and the third subcell on the other side, and the second graded interlayer is compositionally graded to lattice match the third subcell on one side and the bottom fourth subcell on the other side. 12. A method as defined in claim 9 , wherein said first graded interlayer is composed of any of the As, N, Sb based III-V compound semiconductors subject to the constraints of having the in-plane lattice parameter greater or equal to that of the second subcell and less than or equal to that of the third subcell, and having a band gap energy greater than that of the second subcell and of the third subcell. 13. A method as defined in claim 9 , wherein said second graded interlayer is composed of any of the As, N, Sb based III-V compound semiconductors subject to the constraints of having the in-plane lattice parameter greater or equal to that of the third subcell and less than or equal to that of the bottom fourth subcell, and having a band gap energy greater than that of the third subcell and of the fourth subcell. 14. A method as defined in claim 9 , wherein the first and second graded interlayers are composed of (In x Ga 1-x ) y Al 1-y As with x and y selected such that the band gap of each interlayer remains constant throughout its thickness. 15. A method as defined in claim 9 , wherein the band gap of the first graded interlayer remains constant at 1.5 eV, and the band gap of the second graded interlayer remains constant at 1.1 eV. 16. A method as defined in claim 9 , wherein the first subcell is composed of an InGaP emitter layer and an InGaP base layer, the second subcell is composed of an InGaP emitter layer and a GaAs base layer, the third subcell is composed of an InGaP emitter layer and an InGaAs base layer, and the bottom fourth subcell is composed of an InGaAs base layer and an InGaAs emitter layer lattice matched to the base layer.
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