MOSFETs with multiple dislocation planes

Patent metadata

Field	Value
Publication number	US-9853157-B2
Application number	US-201615082250-A
Country	US
Kind code	B2
Filing date	Mar 28, 2016
Priority date	Oct 24, 2011
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.

First claim

What is claimed is:

1. A device comprising:
a semiconductor region having a top surface;
a gate electrode comprising a portion over the semiconductor region;
a source/drain region adjacent to the gate electrode;
a first dislocation plane adjacent to the gate electrode and in the semiconductor region;
a second dislocation plane un-parallel to the first dislocation plane, wherein both the first dislocation plane and the second dislocation plane extend into the source/drain region, and both the first dislocation plane and the second dislocation plane have lower portions increasingly closer to a middle vertical line of the gate electrode than respective upper portions; and
an isolation region extending into the semiconductor region, wherein the isolation region has a first top surface and a second top surface lower than the first top surface, with the second top surface being between the first top surface and the semiconductor region, and a pitch-off line of the first dislocation plane is higher than the second top surface of the isolation region.

2. The device of claim 1 , wherein the first dislocation plane has a first tilt angle, and the second dislocation plane has a second tilt angle greater than the first tilt angle, and the second dislocation plane is farther away from the gate electrode than the first dislocation plane, and both the first tilt angle and the second tilt angle are smaller than 90 degrees, and the first tilt angle is formed between the first dislocation plane and the top surface, and the second tilt angle is formed between the second dislocation plane and the top surface.

3. The device of claim 1 , wherein the first dislocation plane has a first tilt angle, and the second dislocation plane has a second tilt angle smaller than the first tilt angle, and the second dislocation plane is farther away from the gate electrode than the first dislocation plane, and both the first tilt angle and the second tilt angle are smaller than 90 degrees, and the first tilt angle is formed between the first dislocation plane and the top surface, and the second tilt angle is formed between the second dislocation plane and the top surface.

4. The device of claim 1 further comprising a third dislocation plane un-parallel to both the first dislocation plane and the second dislocation plane, wherein the third dislocation plane extends into the source/drain region.

5. The device of claim 1 , wherein the first dislocation plane is joined to the second dislocation plane.

6. The device of claim 1 further comprising:
a main spacer on a sidewall of the gate electrode, wherein the main spacer comprises a material selected from the group consisting essentially of silicon oxide, silicon nitride, and combinations thereof; and
a first offset spacer on an outer sidewall of the main spacer, wherein the first offset spacer comprises hydrogen.

7. The device of claim 6 further comprising:
a second offset spacer on an outer sidewall of the first offset spacer, wherein the second offset spacer comprises hydrogen, and a hydrogen percentage in the second offset spacer is different from a hydrogen percentage in the first offset spacer.

8. A device comprising:
a semiconductor region;
a gate electrode comprising a portion over the semiconductor region;
a source/drain region on a side of the gate electrode and in the semiconductor region;
a main spacer having an inner sidewall contacting a sidewall of the gate electrode, wherein the main spacer is substantially free from hydrogen;
a first offset spacer having an inner sidewall contacting an outer sidewall of the main spacer, wherein the first offset spacer comprises hydrogen; and
a first dislocation plane extending into the source/drain region, wherein the first dislocation plane has a first tilt angle smaller than about 45 degrees, with the first tilt angle being an angle between the first dislocation plane and a top surface of a semiconductor region.

9. The device of claim 8 , wherein the first tilt angle is between about 20 degrees and about 40 degrees.

10. The device of claim 8 further comprising, wherein and entirety of the first dislocation plane is in the semiconductor region.

11. The device of claim 8 further comprising a second dislocation plane extending into the source/drain region, wherein both the first dislocation plane and the second dislocation plane have lower portions increasingly closer to a middle vertical line of the gate electrode than respective upper portions, wherein the second dislocation plane is fully in the source/drain region, and the first dislocation plane comprises a first portion in the source/drain region, and a second portion outside of the source/drain region.

12. The device of claim 8 further comprising a second offset spacer having an inner sidewall contacting an outer sidewall of the first offset spacer, wherein the second offset spacer has a hydrogen percentage different from a hydrogen percentage in the first offset spacer.

13. The device of claim 8 further comprising:
a second dislocation plane extending into the source/drain region, wherein the second dislocation plane is un-parallel to the first dislocation plane, and both the first dislocation plane and the second dislocation plane have lower portions increasingly closer to a middle vertical line of the gate electrode than respective upper portions.

14. The device of claim 13 , wherein the second dislocation plane is farther from the gate electrode than the first dislocation plane, and the second dislocation plane has a second tilt angle smaller than the first tilt angle, with the second tilt angle being an angle between the second dislocation plane and the top surface of a semiconductor region.

15. The device of claim 13 , wherein the second dislocation plane is farther away from the gate electrode than the first dislocation plane, and the second dislocation plane has a second tilt angle greater than the first tilt angle, and both the first tilt angle and the second tilt angle are smaller than 90 degrees, and the first tilt angle is formed between the first dislocation plane and a horizontal top surface of the semiconductor region, and the second tilt angle is formed between the second dislocation plane and the horizontal top surface.

16. The device of claim 13 , wherein the second dislocation plane is farther away from the gate electrode than the first dislocation plane, and the second dislocation plane has a second tilt angle smaller than the first tilt angle, and both the first tilt angle and the second tilt angle are smaller than 90 degrees, and the first tilt angle is formed between the first dislocation plane and a horizontal top surface of the semiconductor region, and the second tilt angle is formed between the second dislocation plane and the horizontal top surface.

17. A device comprising:
a semiconductor region;
a gate electrode comprising a portion over the semiconductor region;
a source/drain region on a side of the gate electrode and in the semiconductor region;
a first dislocation plane extending into the source/drain region;
a second dislocation plane extending into the source/drain region;
a third dislocation plane extending into the source/drain region, wherein two of the first dislocation plane, the second dislocation plane, and the third dislocation plane are un-parallel to each other; and
an isolation region having a sidewall contacting a sidewall of the semiconductor region, with the isolation region having a recess, and both a sidewall of the isolation region and a sidewall of the source/drain region are exposed

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Wei-Yuan

Classifications

• H10P36/03

  within silicon bodies · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title