Method of modifying the strain state of a semiconducting structure with stacked transistor channels

Patent metadata

Field	Value
Publication number	US-9853130-B2
Application number	US-201615049468-A
Country	US
Kind code	B2
Filing date	Feb 22, 2016
Priority date	Feb 24, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A method of modifying a strain state of a first channel structure in a transistor is provided, said structure being formed from superposed semiconducting elements, the method including providing on a substrate at least one first semiconducting structure formed from a semiconducting stack including alternating elements based on at least one first semiconducting material and elements based on at least one second semiconducting material different from the first material; then removing portions of the second material from the first semiconducting structure by selective etching, the removed portions forming at least one empty space; filling the empty space with a dielectric material; forming a straining zone on the first semiconducting structure based on a first strained material having an intrinsic strain; and performing thermal annealing to cause the dielectric material to creep, and to cause a change in a strain state of the elements based on the first material.

First claim

The invention claimed is:

1. A method of modifying a strain state of a first channel structure in at least one first transistor, the first channel structure being formed from superposed semiconducting elements, the method comprising:
a) providing at least one first semiconducting structure on a substrate, said structure being formed from a semiconducting stack comprising alternating elements based on at least one first semiconducting material and elements based on at least one second semiconducting material different from the at least one first semiconducting material; then
b) removing portions of the at least one second semiconducting material from the at least one first semiconducting structure by selective etching, the removed portions of the at least one second semiconducting material forming at least one empty space;
c) filling the at least one empty space with a dielectric material;
d) forming a straining zone on the at least one first semiconducting structure based on a first strained material having an intrinsic strain; and
e) performing thermal annealing to cause the dielectric material to creep, and to cause a change in a strain state of the elements based on the at least one first semiconducting material in the at least one first semiconducting structure.

2. The method according to claim 1 ,
wherein the substrate is a strained semiconductor-on-insulator type substrate including a strained surface semiconducting layer, and
wherein the change in the stain state in step e) is relaxation of the elements based on the at least one first semiconducting material.

3. The method according to claim 1 ,
wherein the substrate is a strained semiconductor-on-insulator type substrate including a relaxed surface semiconducting layer, and
wherein the change in the strait state in step e) is an increase in a strain state induced by the straining zone in the elements based on the at least one first semiconducting material.

4. The method according to claim 1 , wherein the dielectric material is based on SiO 2 or a doped silicon oxide.

5. The method according to claim 1 , wherein the at least one first semiconducting material is Si and the at least one second semiconducting material is Si 1−y Ge y , where 0<y<1, or the at least one second semiconducting material is Si and the at least one first semiconducting material is Si 1−x Ge x , where 0<x<1.

6. The method according to claim 1 , further comprising after step e), removing the straining zone while maintaining a strain state of the dielectric material that has undergone creep.

7. The method according to claim 1 ,
further comprising providing at least one second transistor having a second channel structure formed from superposed semiconducting elements, and at least one second semiconducting structure formed in the semiconducting stack,
wherein the at least one second semiconducting structure formed in the semiconducting stack comprises alternating elements based on the at least one first semiconducting material and elements based on the at least one second semiconducting material different from the first semiconducting material provided in step a), and
wherein step d) further comprises:
depositing the first strained material on the at least one first semiconducting structure and on the at least one second semiconducting structure, then
removing the first strained material from the at least one second semiconducting structure.

8. The method according to claim 7 , further comprising forming another straining zone on the at least one second semiconducting structure based on a second strained material having an intrinsic strain opposite to the intrinsic strain of the first strained material.

9. The method according to claim 7 ,
wherein the at least one first semiconducting structure and the at least one second semiconducting structure are attached to each other by at least one anchor block, and
wherein the at least one anchor block is removed before step e).

10. The method according to claim 9 , wherein the at least one anchor block is removed after step d) by etching where the straining zone is used as a protective stencil for the etching.

Assignees

• Commissariat Energie Atomique
• Commissariat á l'énergie atomique et aux énergies alternatives

Inventors

• Maitrejean Sylvain
• Augendre Emmanuel
• Barbe Jean-Charles
• Mathieu Benoit
• Morand Yves

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L21/3065

  Electricity · mapped topic

• H01L21/31144

  Electricity · mapped topic