Strained nanowire CMOS device and method of forming

Patent metadata

Field	Value
Publication number	US-9853101-B2
Application number	US-201514935195-A
Country	US
Kind code	B2
Filing date	Nov 6, 2015
Priority date	Oct 7, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first fin and a second fin, each of the first fin and the second fin comprising an alternating epitaxial structure, the alternating epitaxial structure having a plurality of epitaxial layers, the plurality of epitaxial layers comprising first epitaxial layers and second epitaxial layers, the first epitaxial layers comprising a first semiconductor material, the second epitaxial layers comprising a second semiconductor material, layers of the alternating epitaxial structure alternating between one of the first epitaxial layers and one of the second epitaxial layers;
forming a first dielectric layer over the first fin and the second fin;
exposing a channel region of the second fin;
removing at least a portion of the first epitaxial layers in the channel region of the second fin;
forming a first gate stack over the first fin, the first gate stack extending along sidewalls of the first epitaxial layers and the second epitaxial layers of the first fin; and
forming a second gate stack over the second fin, the second gate stack extending along sidewalls of the second epitaxial layers.

2. The method of claim 1 , wherein removing at least a portion of the first epitaxial layers completely removes the first epitaxial layers between adjacent second epitaxial layers in the channel region.

3. The method of claim 1 , wherein the first gate stack and the second gate stack are a same gate stack.

4. The method of claim 1 , wherein the first fin comprises a channel region of a p-type transistor and the second fin comprises a channel region of an n-type transistor.

5. The method of claim 1 , further comprising:
forming a strain relaxed buffer (SRB) over a substrate;
forming the alternating epitaxial structure over the SRB; and
forming trenches in the alternating epitaxial structure, the trenches extending at least partially into the SRB, wherein the first fin and the second fin are interposed between adjacent trenches.

6. The method of claim 5 , wherein the trenches extend completely through the SRB.

7. The method of claim 5 , wherein removing at least a portion of the first epitaxial layers comprises separating a lowermost second epitaxial layer of the second epitaxial layers from the SRB in the channel region.

8. The method of claim 1 , further comprising:
after forming the first dielectric layer, exposing an uppermost second epitaxial layer of the second epitaxial layers of the first fin; and
removing the uppermost second epitaxial layer of the second epitaxial layers of the first fin, wherein the second gate stack extends over an upper surface of an uppermost first epitaxial layer of the first fin.

9. The method of claim 1 , wherein removing at least a portion of the first epitaxial layers comprises forming V-shaped indents along sidewalls of the first epitaxial layers.

10. The method of claim 1 , wherein removing at least a portion of the first epitaxial layers comprises forming U-shaped indents along sidewalls of the first epitaxial layers.

11. The method of claim 1 , wherein removing at least a portion of the first epitaxial layers comprises recessing the sidewalls of the first epitaxial layers.

12. A method of forming a semiconductor device, the method comprising:
forming a first fin and a second fin, each of the first fin and the second fin comprising an alternating epitaxial structure, the alternating epitaxial structure having a plurality of epitaxial layers, the plurality of epitaxial layers comprising first epitaxial layers and second epitaxial layers, the first epitaxial layers comprising a first semiconductor material, the second epitaxial layers comprising a second semiconductor material, layers of the alternating epitaxial structure alternating between one of the first epitaxial layers and one of the second epitaxial layers;
selectively etching sidewalls of at least one of the first epitaxial layers in a first channel region of the first fin;
selectively etching sidewalls of at least one of the second epitaxial layers in a second channel region of the second fin;
forming a first gate stack over the first fin; and
forming a second gate stack over the second fin.

13. The method of claim 12 , wherein selectively etching sidewalls of at least one of the first epitaxial layers completely removes all of the first epitaxial layers.

14. The method of claim 12 , wherein selectively etching sidewalls of at least one of the first epitaxial layers comprises:
removing a lowermost first epitaxial layer of the first epitaxial layers in the first channel region; and
selectively etching sidewalls of remaining ones of the first epitaxial layers in the first channel region.

15. The method of claim 14 , wherein selectively etching sidewalls of remaining ones of the first epitaxial layers comprises forming V-shaped indents along sidewalls of the first epitaxial layers.

16. The method of claim 14 , wherein selectively etching sidewalls of remaining ones of the first epitaxial layers comprises forming U-shaped indents along sidewalls of the first epitaxial layers.

17. The method of claim 14 , wherein selectively etching sidewalls of remaining ones of the first epitaxial layers comprises recessing the sidewalls of the first epitaxial layers.

18. The method of claim 12 , further comprising:
forming a strain relaxed buffer (SRB) over a substrate;
forming the alternating epitaxial structure over the SRB; and
forming trenches in the alternating epitaxial structure, the trenches extending at least partially into the SRB, wherein the first fin and the second fin are interposed between adjacent trenches.

19. The method of claim 18 , wherein selectively etching sidewalls of at least one of the first epitaxial layers in a first channel region of the first fin comprises forming an opening through the first fin.

20. A method of forming a semiconductor device, the method comprising:
forming a first fin and a second fin, each of the first fin and the second fin comprising an alternating epitaxial structure, the alternating epitaxial structure having a plurality of epitaxial layers, the plurality of epitaxial layers comprising first epitaxial layers and second epitaxial layers, the first epitaxial layers comprising a first semiconductor material, the second epitaxial layers comprising a second semiconductor material, layers of the alternating epitaxial structure alternating between one of the first epitaxial layers and one of the second epitaxial layers;
indenting sidewalls of the first epitaxial layers from sidewalls of the second epitaxial layers in a first channel region of the first fin;
indenting sidewalls of the second epitaxial layers from sidewalls of the first epitaxial layer in a second channel region of the second fin;
forming a first gate stack over the first fin; and
forming a second gate stack over the second fin.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Cheng-Yi
• Chiang Hung-Li
• Yang Yu-Lin
• Yeh Chih Chieh
• Yeo Yee-Chia
• Liu Chi-Wen

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H01L27/0924

  Electricity · mapped topic