Magnetoresistive random access memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9853087-B2
Application number	US-201615157403-A
Country	US
Kind code	B2
Filing date	May 17, 2016
Priority date	Sep 8, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

First claim

What is claimed is:

1. A method of manufacturing a magnetoresistive random access memory (MRAM) device, comprising:
sequentially forming a first insulating interlayer and an etch-stop layer on a substrate;
after forming the etch-stop layer forming a lower electrode through the etch-stop layer and the first insulating interlayer, the lower electrode extending in both of the etch-stop layer and the first insulating interlayer;
sequentially forming a magnetic tunnel junction (MTJ) structure layer and an upper electrode on the lower electrode and the etch-stop layer; and
patterning the MTJ structure layer by a physical etching process using the upper electrode as an etching mask to form an MTJ structure that at least partially contacts the lower electrode, wherein the first insulating interlayer is protected by the etch-stop layer so as not to be etched by the physical etching process.

2. The method of claim 1 , wherein the etch-stop layer includes a metal oxide, a nitride, a ceramic material, or a combination thereof.

3. The method of claim 2 , wherein the metal oxide includes aluminum oxide, magnesium oxide, yttrium oxide, erbium oxide, or a combination thereof.

4. The method of claim 2 , wherein the nitride includes boron nitride.

5. The method of claim 2 , wherein the ceramic material includes yttrium silicon oxide, zirconium titanium oxide, barium titanium oxide, or a combination thereof.

6. The method of claim 1 , wherein the physical etching process includes an ion beam etching (IBE) process.

7. The method of claim 1 , wherein at least a portion of the etch-stop layer remains on the first insulating interlayer after the physical etching process.

8. The method of claim 1 , wherein the MTJ structure covers an entire upper surface of the lower electrode.

9. The method of claim 1 , wherein the MTJ structure covers a portion of an upper surface of the lower electrode,
and wherein a recess is formed at an upper portion of the lower electrode by the physical etching process, a bottom of the recess not being lower than a lower surface of the etch-stop layer.

10. The method of claim 1 , wherein forming the lower electrode includes forming a landing pad through the etch-stop layer and the first insulating interlayer that is spaced apart from the lower electrode.

11. The method of claim 10 , wherein forming the lower electrode and the landing pad includes:
forming first and second openings through the etch-stop layer and the first insulating interlayer;
forming a conductive layer on the etch-stop layer to fill the first and second openings; and
planarizing the conductive layer until an upper surface of the etch-stop layer is exposed.

12. The method of claim 11 , wherein upper surfaces of the lower electrode and the landing pad are substantially higher than the upper surface of the etch-stop layer.

13. A method of manufacturing a magnetoresistive random access memory (MRAM) device, comprising:
forming an insulating interlayer structure on a substrate, the insulating interlayer structure including a first insulating interlayer, an etch-stop layer, and a second insulating interlayer sequentially stacked;
after forming the insulating interlayer structure, forming a lower electrode through the insulating interlayer structure, the lower electrode extending in all of the first insulating interlayer, the etch-stop layer and the second insulating interlayer;
sequentially forming a magnetic tunnel junction (MTJ) structure layer and an upper electrode on the lower electrode and the insulating interlayer structure; and
patterning the MTJ structure layer by a physical etching process using the upper electrode as an etching mask to form an MTJ structure that at least partially contacts the lower electrode, wherein a portion of the insulating interlayer structure under the etch-stop layer is substantially protected by the etch-stop layer so as not to be etched by the physical etching process.

14. The method of claim 13 , wherein the at least a portion of the etch-stop layer remains on the first insulating interlayer after the physical etching process.

15. A method to form a magnetoresistive random access memory (MRAM) device, the method comprising:
forming a first insulating interlayer on a top surface of a substrate, the first insulating interlayer comprising a bottom surface and a top surface that is opposite the bottom surface, the bottom surface of the first insulating interlayer being proximate to the top surface of the substrate, and the top surface of the first insulating interlayer being distal to the top surface of the substrate;
forming at least one first wiring structure in the first insulating interlayer, the at least one first wiring structure comprising a top surface, and at least a portion of the top surface of the at least one first wiring structure being at substantially a same level at the top surface of the first insulating interlayer;
forming an etch-stop layer on the top surface of the first insulating interlayer, the etch-stop layer comprising a bottom surface and a top surface that is opposite the bottom surface, the bottom surface of the etch-stop layer being proximate to the top surface of the first insulating interlayer, the top surface of the etch-stop layer being distal to the top surface of the first insulating interlayer, and the bottom surface of the etch-stop layer being lower than the top surface of the at least one first wiring structure;
forming a second insulating interlayer on the top surface of the etch-stop layer, the second insulating interlayer comprising a bottom surface and a top surface that is opposite the bottom surface, the bottom surface of the second insulating interlayer being proximate to the top surface of the etch-stop layer, and the top surface of the first insulating interlayer being distal to the top surface of the etch-stop layer;
forming at least one lower electrode disposed in the second insulating interlayer, the at least one lower electrode extending through the second insulating interlayer and contacting a corresponding first wiring structure; and
forming at least one magnetic tunnel junction (MTJ) structure, each MTJ structure being electrically connected to a corresponding to a lower electrode.

16. The method of claim 15 , further comprising forming a plurality of MTJ structures arranged in an array comprising at least one row and at least one column.

17. The method of claim 15 , wherein the etch-stop layer comprises a metal oxide, a nitride, a ceramic material, or a combination thereof.

18. The method of claim 15 , further comprising:
forming a third insulating interlayer on the top surface of the second insulating interlayer, the third insulating interlayer comprising a bottom surface and a top surface that is opposite the bottom surface, the bottom surface of the third insulating interlayer being proximate to the top surface of the second insulating interlayer, and the top surface of the third insulating interlayer being distal to the top surface of the second insulating interlayer; and
forming at least one third wiring structure disposed in the third insulating interlayer, the at least one third wiring structure being electrically connected to a corresponding MTJ structure.

19. The method of claim 15 , further comprising:
forming at least one landing pad disposed in the first insulating interlayer, the at least one landing pad comprising a top surface, and at least a portion of the top surface of the at least one landing pad being at substantially a higher level as the top su

Assignees

• Suh Ki-Seok
• Shim Jae-Chul
• Lee Kil-Ho
• Chung Yong-Seok
• Koh Gwan-Hyeob
• Song Yoon-Jong
• Samsung Electronics Co Ltd

Inventors

• Suh Ki-Seok
• Shim Jae-Chul
• Lee Kil-Ho
• Chung Yong-Seok
• Koh Gwan-Hyeob
• Song Yoon-Jong

Classifications

• H01L27/222 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/01

  Manufacture or treatment · CPC title