Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9853069-B2
Application number	US-201715629970-A
Country	US
Kind code	B2
Filing date	Jun 22, 2017
Priority date	Oct 22, 2008
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a transistor;
a terminal portion;
a first metal layer and a second metal layer, the first metal layer and the second metal layer comprising copper;
a first insulating layer over the first metal layer and the second metal layer;
an oxide semiconductor film over the first insulating layer;
a third metal layer and a fourth metal layer over the first insulating layer, the third metal layer and the fourth metal layer comprising copper;
a second insulating layer over the oxide semiconductor film, the third metal layer and the fourth metal layer; and
a pixel electrode and an electrode over the second insulating layer, wherein the pixel electrode and the electrode are transparent,
wherein the first metal layer and the second metal layer are formed by a stack of a first titanium film and a first copper film,
wherein the third metal layer is electrically connected to the oxide semiconductor film,
wherein the oxide semiconductor film comprises a channel region of the transistor,
wherein the first metal layer comprises a gate electrode of the transistor,
wherein the fourth metal layer is directly in contact with the second metal layer through a first contact hole of the first insulating layer,
wherein the pixel electrode is electrically connected to the third metal layer,
wherein the electrode is electrically connected to the second metal layer through the fourth metal layer, and
wherein the terminal portion comprises the second metal layer, the fourth metal layer, and the electrode.

2. The semiconductor device according to claim 1 ,
wherein the electrode is electrically connected to the fourth metal layer through a second contact hole of the second insulating layer,
wherein a location of the first contact hole is different from a location of the second contact hole.

3. The semiconductor device according to claim 1 ,
wherein the third metal layer covers the oxide semiconductor film and is in direct contact with one of sides edge of the oxide semiconductor film.

4. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor film comprises a first semiconductor layer and a second semiconductor layer,
wherein the second semiconductor layer is over the first semiconductor layer and is stacked on the first semiconductor layer.

5. The semiconductor device according to claim 4 ,
wherein the second semiconductor layer is not stacked on the first semiconductor layer on the channel region.

6. The semiconductor device according to claim 1 ,
wherein the first insulating layer comprises aluminum or tantalum.

7. The semiconductor device according to claim 1 ,
wherein the second insulating layer comprises aluminum or tantalum.

8. The semiconductor device according to claim 1 ,
wherein the third metal layer and the fourth metal layer are formed by a stack of a second titanium film and a second aluminum film.

9. A semiconductor device comprising:
a transistor;
a terminal portion;
a first metal layer and a second metal layer;
a first insulating layer over the first metal layer and the second metal layer, the first metal layer and the second metal layer comprising copper;
an oxide semiconductor film over the first insulating layer;
a third metal layer and a fourth metal layer over the first insulating layer, the third metal layer and the fourth metal layer comprising copper;
a second insulating layer over the oxide semiconductor film, the third metal layer and the fourth metal layer; and
a pixel electrode and an electrode over the second insulating layer, wherein the pixel electrode and the electrode are transparent,
wherein the first metal layer and the second metal layer are formed by a stack of a first titanium film and a first copper film,
wherein the third metal layer is electrically connected to the oxide semiconductor film,
wherein the oxide semiconductor film comprises a channel region of the transistor,
wherein the oxide semiconductor film comprises a region overlapping the third metal layer,
wherein a thickness of the channel region is thinner than the region,
wherein the first metal layer comprises a gate electrode of the transistor,
wherein the fourth metal layer is directly in contact with the second metal layer through a first contact hole of the first insulating layer,
wherein the pixel electrode is electrically connected to the third metal layer,
wherein the electrode is electrically connected to the second metal layer through the fourth metal layer, and
wherein the terminal portion comprises the second metal layer, the fourth metal layer, and the electrode.

10. The semiconductor device according to claim 9 ,
wherein the third metal layer covers the oxide semiconductor film and is in direct contact with one of sides edge of the oxide semiconductor film.

11. The semiconductor device according to claim 9 ,
wherein the oxide semiconductor film comprises a first semiconductor layer and a second semiconductor layer,
wherein the second semiconductor layer is over the first semiconductor layer and is stacked on the first semiconductor layer.

12. The semiconductor device according to claim 11 ,
wherein the second semiconductor layer is not stacked on the first semiconductor layer on the channel region.

13. The semiconductor device according to claim 9 ,
wherein the first insulating layer comprises aluminum or tantalum.

14. The semiconductor device according to claim 9 , wherein the second insulating layer comprises aluminum or tantalum.

15. The semiconductor device according to claim 9 ,
wherein the third metal layer and the fourth metal layer is formed by a stack of a titanium film and an aluminum film.

16. A semiconductor device comprising:
a transistor;
a terminal portion;
a first metal layer and a second metal layer, the first metal layer and the second metal layer comprising copper;
a first insulating layer over the first metal layer and the second metal layer;
an oxide semiconductor film over the first insulating layer;
a third metal layer and a fourth metal layer over the first insulating layer, the third metal layer and the fourth metal layer comprising copper;
a second insulating layer over the oxide semiconductor film, the third metal layer and the fourth metal layer; and
a pixel electrode and an electrode over the second insulating layer, wherein the pixel electrode and the electrode are transparent,
wherein the first metal layer and the second metal layer are formed by a stack of a first titanium film and a first copper film,
wherein the third metal layer is electrically connected to the oxide semiconductor film,
wherein the oxide semiconductor film comprises a channel region of the transistor,
wherein the oxide semiconductor film comprises a region overlapping the third metal layer,
wherein a thickness of the channel region is thinner than the region,
wherein the second insulating layer is directly in contact with the channel region,
wherein the first metal layer comprises a gate electrode of the transistor,
wherein the fourth metal layer is directly in contact with the second metal layer through a first contact hole of the first insulating layer,
wherein the pixel electrode is electrically connected to the third metal layer,
wherein the electrode is electrically connected to the second metal layer through the fourth metal layer, and
wherein the terminal portion comprises the second metal layer, the fourth metal layer, and the electrode.

17. The semiconductor device according to claim 16 ,
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Assignees

• Semiconductor Energy Lab

Inventors

• Suzawa Hideomi
• Sasagawa Shinya
• Muraoka Taiga

Classifications

• H10P95/70

  Chemical treatments · CPC title

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/20

  Dry etching; Plasma etching; Reactive-ion etching · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title