Integrated circuit device body bias circuits and methods

Patent metadata

Field	Value
Publication number	US-9853019-B2
Application number	US-201615337876-A
Country	US
Kind code	B2
Filing date	Oct 28, 2016
Priority date	Mar 15, 2013
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

First claim

What is claimed is:

1. A method, comprising:
supplying a first power supply voltage for a charge pump circuit that generates a global body bias voltage;
generating a local body bias voltage from the global body bias voltage;
waiting for a predetermined delay after the local body bias voltage reaching and being stable at a predetermined value, and then supplying a second power supply voltage applied for transistors having the local body bias voltage while the local body bias voltage is stable at the predetermined value, the second power supply voltage being lower than the first power supply voltage.

2. The method of claim 1 , further including:
in response to at least one local event and in response to a global event, coupling bodies of the transistors to a collapse voltage that tracks the first power supply voltage.

3. The method of claim 1 , wherein:
the transistors including deeply depleted channel (DDC) transistors, each DDC transistor comprises a body with a screening region of a dopant concentration of no less than 1×10 18 dopant atoms/cm 3 formed below a transistor channel.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Clark Lawrence T
• Kidd David A
• Kuo Augustine

Classifications

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H03K3/012

  Modifications of generator to improve response time or to decrease power consumption · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H03K17/063

  in field-effect transistor switches · CPC title

• G05F3/205

  Substrate bias-voltage generators (for static stores G11C5/146) · CPC title