Systems and methods for high-speed, low-profile memory packages and pinout designs

Patent metadata

Field	Value
Publication number	US-9853016-B2
Application number	US-201715435719-A
Country	US
Kind code	B2
Filing date	Feb 17, 2017
Priority date	Mar 13, 2013
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

First claim

What is claimed is:

1. A method for manufacturing a stacked semiconductor package, the method comprising:
providing an integrated circuit (“IC”) package substrate comprising a plurality of conductive contacts formed on a surface of the IC package substrate, wherein the plurality of conductive contacts further comprise a plurality of data I/O contacts and a plurality of ground (“GND”) contacts, wherein only two GND contacts of the plurality of GND contacts are surrounded by the data I/O contacts associated with respective ones of the first and second subsets of the plurality conductive contacts;
physically coupling an stack of memory dies to a top surface of the IC package substrate in an arrow-shaped stack;
electrically coupling bond pads provided on exposed surfaces of the memory dies in a first half of the arrow-shaped stack to contacts of the IC package substrate associated with a first communications channel; and
electrically coupling bond pads provided on exposed surfaces of the memory dies in a second half of the arrow-shaped stack to contacts of the IC package substrate associated with a second communications channel.

2. The method of claim 1 , further comprising:
forming a plurality of electrically conductive vias through the IC package substrate that extend from the top surface of the IC package substrate to a bottom surface of the IC package substrate.

3. The method of claim 2 , further comprising an array of electrical contacts formed on the bottom surface of the IC package substrate, the array of electrical contacts being communicatively coupled to the bond pads using the plurality of electrically conductive vias.

4. The method of claim 3 , wherein a first subset of the array of electrical contacts formed on a first side of the bottom surface of the IC package substrate corresponds to the first communications channel, and wherein a second subset of the array of electrical contacts formed on a second side of the bottom surface of the IC package substrate corresponds to the second communications channel.

5. The method of claim 1 , further comprising coupling an IC die between the top surface of the IC package substrate and the stack of memory dies.

6. The method of claim 5 , wherein the coupling the IC die comprises flip chip bonding the IC die to the top surface of the IC package substrate.

7. The method of claim 5 , wherein the coupling the IC die comprises wire bonding the IC die to bond pads formed on the top surface of the IC package substrate.

8. The method of claim 1 , further comprising coupling an electromagnetic interference (“EMI”) shield to the stacked semiconductor package.

9. The method of claim 8 , further comprising filling space between the EMI shield and the IC package substrate with a dielectric material.

10. A method for manufacturing a stacked semiconductor package, the method comprising:
providing an integrated circuit (“IC”) package substrate comprising an array of contacts, the array of contacts comprising a plurality of data I/O contacts formed on a surface of the IC package substrate, wherein:
a first subset of the plurality of data I/O contacts forms a first C-shaped layout arranged on a first portion of the bottom surface;
a second subset of the plurality of data I/O contacts forms a second C-shaped layout arranged on a second portion of the bottom surface; and
the first portion and the second portion are reflectively symmetrical about a central axis;

physically coupling an stack of memory dies to a top surface of the IC package substrate in an arrow-shaped stack;
electrically coupling bond pads provided on exposed surfaces of the memory dies in a first half of the arrow-shaped stack to contacts of the IC package substrate associated with a first communications channel; and
electrically coupling bond pads provided on exposed surfaces of the memory dies in a second half of the arrow-shaped stack to contacts of the IC package substrate associated with a second communications channel.

11. The method of claim 10 , wherein the array of contacts further comprising a plurality of ground (“GND”) contacts, wherein at least one GND contact of the plurality of GND contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.

12. The method of claim 10 , wherein the array of contacts further comprising a plurality of data queue stroke (“DQS”) contacts, wherein at least one DQS contact of the plurality of DQS contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.

13. The method of claim 10 , further comprising:
forming a plurality of electrically conductive vias through the IC package substrate that extend from the top surface of the IC package substrate to a bottom surface of the IC package substrate.

14. The method of claim 13 , further comprising an array of electrical contacts formed on the bottom surface of the IC package substrate, the array of electrical contacts being communicatively coupled to the bond pads using the plurality of electrically conductive vias.

15. The method of claim 14 , wherein a first subset of the array of electrical contacts formed on a first side of the bottom surface of the IC package substrate corresponds to the first communications channel, and wherein a second subset of the array of electrical contacts formed on a second side of the bottom surface of the IC package substrate corresponds to the second communications channel.

16. The method of claim 10 , further comprising coupling an IC die between the top surface of the IC package substrate and the stack of memory dies.

Assignees

• Apple Inc

Inventors

• Fai Anthony
• Boyle Evan R
• Yang Zhiping
• Wu Zhonghua

Classifications

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W42/271

  the arrangements being between stacked chips · CPC title