Semiconductor device having stacked chips

Patent metadata

Field	Value
Publication number	US-9853013-B2
Application number	US-201615232391-A
Country	US
Kind code	B2
Filing date	Aug 9, 2016
Priority date	Sep 6, 2012
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, wherein these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, and includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first chip having a first via and a second via through the first chip; and
a second chip provided on the first chip and having a third via and a fourth via through the second chip;
wherein the first chip includes:
a first inversion circuit, the first inversion circuit being configured to invert a first address signal to an first inverted address signal and supply the first inverted address signal to the second chip through the first via;
a first logical operation circuit connected to the first inversion circuit, the first logical operation circuit being configured to perform a logical operation on a second address signal and the first inverted address signal, and supply a first arithmetic operation output signal to the second chip through the second via; and
a first selection circuit connected to the first logical operation circuit, the first selection circuit being configured to select a chip based on at least the first arithmetic operation output signal.

2. The device according to claim 1 , further comprising:
a third chip provided on the second chip;
wherein the second chip includes:
a second inversion circuit connected to the first via, the second inversion circuit being configured to invert the first inverted address signal to a second inverted address signal and supply the second inverted address signal to the third chip through the third via;
a second logical operation circuit connected to the second via and the second inversion circuit, the second logical operation circuit being configured to perform a logical operation on the first arithmetic operation output signal and the second inverted address signal, and supply a second arithmetic operation output signal to the third chip through the fourth via; and
a second selection circuit connected to the second logical operation circuit, the second selection circuit being configured to select a chip based on at least the second arithmetic operation output signal.

3. The device according to claim 1 , wherein:
the first chip has a fifth via and a sixth via through the first chip,
the second chip has a seventh via and an eighth via through the second chip, the seventh via being connected to the fifth via and the eighth via being connected to the sixth via,
the fifth and seventh vias are configured to transmit a first chip enable signal, and
the sixth and eighth vias are configured to transmit a second chip enable signal.

4. The device according to claim 3 , wherein the first selection circuit is configured to select a chip based on the first chip enable signal and the second chip enable signal in addition to the first arithmetic operation output signal.

5. The device according to claim 2 , wherein:
the first chip has a fifth via and a sixth via through the first chip,
the second chip has a seventh via and an eighth via through the second chip, the seventh via being connected to the fifth via and the eighth being via connected to the sixth via,
the fifth and seventh vias are configured to transmit a first chip enable signal, and
the sixth and eighth vias are configured to transmit a second chip enable signal.

6. The device according to claim 5 , wherein:
the second selection circuit is connected to the fifth and sixth vias, and
the second selection circuit is configured to select a chip based on the first chip enable signal and the second chip enable signal in addition to the second arithmetic operation output signal.

7. The device according to claim 1 , wherein the first logical operation circuit is a XOR circuit.

8. A semiconductor device, comprising:
a package substrate having a first pad and a second pad on a first surface;
an I/F chip provided on the first surface of the package substrate, the I/F chip having a second surface and a third surface, the second surface facing the first surface, the I/F chip having a third pad and a fourth pad on the third surface, the third pad being connected to the first pad, and the second pad being connected to the fourth pad; and
a plurality of stacked chips provided on the I/F chip,
wherein:
the plurality of stacked chips include a first chip and a second chip, each of the first and second chips including a first via, a second via, a third via, a fourth via, a first circuit, a second circuit, and a third circuit,
the first via of the first chip is connected to the first circuit of the first chip,
the first via of the second chip is connected to the first circuit of the second chip,
the first via of the first chip is connected the first via of the second chip,
the second via of the first chip is connected to the second via of the second chip through the second circuit of the second chip,
the third via of the first chip is connected to the third via of the second chip,
the fourth via of the first chip is connected to the fourth via of the second chip,
the third circuit of the second chip is connected to the third and fourth vias of the first chip,
the third pad of the I/F chip is connected to the first via and the second via of the first chip through a fourth circuit in the I/F chip, and
the fourth pad of the I/F circuit is connected to the third via and the fourth via of each of the first chip through a fifth circuit in the I/F chip.

9. The semiconductor device according to claim 8 , wherein:
the fourth circuit is connected to the first via and the second via of the first chip through a rewiring layer, and
the fifth circuit is connected to the third via and the fourth via of the first chip through the rewiring layer.

10. The semiconductor device according to claim 8 , wherein the third circuit of each of the first and second chips is a selection circuit.

Assignees

• Toshiba Memory Corp

Inventors

• Koyanagi Masaru

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/879

  Bump connectors and bond wires · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/859

  Bump connectors and bond wires · CPC title