Semiconductor device and method of aligning semiconductor wafers for bonding

Patent metadata

Field	Value
Publication number	US-9852972-B2
Application number	US-201615218848-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Sep 17, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A semiconductor device has a first semiconductor wafer. The first semiconductor wafer is singulated to provide a first wafer section including at least one first semiconductor die or a plurality of first semiconductor die. The first wafer section is a fractional portion of the first semiconductor wafer. An edge support structure is formed around the first wafer section. A second wafer section includes at least one second semiconductor die. The second wafer section can be an entire second semiconductor wafer. The first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device. An alignment opening is formed through the first wafer section and second wafer section with a light source projected through the opening. The first wafer section is bonded to the second wafer section with the first semiconductor die aligned with the second semiconductor die.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a first semiconductor wafer;
singulating the first semiconductor wafer into a plurality of first wafer sections, wherein each of the plurality of first wafer sections includes a plurality of first semiconductor die;
providing a second wafer section including a plurality of second semiconductor die; and
bonding the plurality of first wafer sections to portions of the second wafer section with the plurality of first semiconductor die each aligned respectively with the plurality of second semiconductor die.

2. The method of claim 1 , wherein each of the first wafer sections is a fractional portion of the first semiconductor wafer.

3. The method of claim 1 , wherein the first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device.

4. The method of claim 1 , wherein the second wafer section is an entire second semiconductor wafer.

5. The method of claim 1 , further including forming an alignment opening through each of the first wafer sections and second wafer section.

6. The method of claim 1 , further including forming an edge support structure around each of the first wafer sections.

7. A method of making a semiconductor device, comprising:
providing a plurality of first wafer sections each including a plurality of first semiconductor die;
providing a second wafer section including a plurality of second semiconductor die; and
bonding the plurality of first wafer sections to the second wafer section to align the first semiconductor die to the second semiconductor die.

8. The method of claim 7 , wherein each of the first wafer sections is a fractional portion of a first semiconductor wafer.

9. The method of claim 7 , wherein the second wafer section is an entire second semiconductor wafer.

10. The method of claim 7 , further including forming an alignment opening through each of the first wafer sections and second wafer section.

11. The method of claim 7 , further including forming an edge support structure around each of the first wafer sections.

12. The method of claim 7 , wherein the first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device.

13. A semiconductor device, comprising:
a plurality of first wafer sections each including a plurality of first semiconductor die; and
a second wafer section including a plurality of second semiconductor die, wherein the first wafer sections are bonded to the second wafer section to align the first semiconductor die to the second semiconductor die.

14. The semiconductor device of claim 13 , wherein each of the first wafer sections is a fractional portion of a first semiconductor wafer.

15. The semiconductor device of claim 13 , wherein the second wafer section is an entire second semiconductor wafer.

16. The semiconductor device of claim 13 , further including an alignment opening formed through each of the first wafer sections and second wafer section.

17. The semiconductor device of claim 13 , further including an edge support structure formed around each of the first wafer sections.

18. The semiconductor device of claim 13 , wherein the first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Seddon Michael J
• Carney Francis J

Classifications

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title