Method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell

Patent metadata

Field	Value
Publication number	US-9852801-B1
Application number	US-201615366662-A
Country	US
Kind code	B1
Filing date	Dec 1, 2016
Priority date	Dec 1, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell, the flash memory cell including a substrate including a channel region; a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric layer; a control gate positioned above the floating gate and separated from the floating gate electrode by the inter-gate dielectric structure; the method including programming the flash memory cell into an initial programmed state and applying biasing conditions to the programmed flash memory cell so as to obtain a zero electric field in the tunnel dielectric layer; measuring over time a change in a threshold voltage of the flash memory cell; and determining the leakage current from the change in the threshold voltage.

First claim

The invention claimed is:

1. A method for determining a leakage current through an inter-gate dielectric structure of a flash memory cell, the flash memory cell comprising:
a substrate comprising a channel region;
a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric layer;
a control gate positioned above the floating gate and separated from the floating gate by the inter-gate dielectric structure;

said method comprising:
programming the flash memory cell into an initial programmed state and applying biasing conditions to the programmed flash memory cell so as to obtain a zero electric field in the tunnel dielectric layer;
measuring over time a change in a threshold voltage of the flash memory cell; and
determining the leakage current from the change in the threshold voltage.

2. The method according to claim 1 , comprising:
determining a flat-band voltage of a tunnel capacitor comprising the channel region, the tunnel dielectric layer and the floating gate, said flat-band voltage implying the zero electric field in the tunnel dielectric layer;
determining the initial programmed state and a corresponding control gate bias that lead to a voltage between the floating gate and the channel region equal to the determined flat-band voltage, given a desired electric field in the inter-gate dielectric structure;
programming the flash memory cell in the initial programmed state;
applying the corresponding control gate bias and read intermittently the programmed flash memory cell so as to obtain a plurality of threshold voltage values of the flash memory cell;
determining the leakage current from the plurality of threshold voltage values.

3. The method according to claim 2 , wherein the flat-band voltage of the tunnel capacitor is determined from a C-V measurement of a capacitive test structure of identical construction but larger area than the tunnel capacitor.

4. The method according to claim 2 , wherein the initial programmed state (V t OSS ) of the flash memory cell and the corresponding control gate bias (V CG OSS ) are determined by solving the following equations:
V t OSS = V CG OSS + V t o - V FB α CG V CG =E ONO ×EOT ONO +V FB

where E ONO is the desired electric field in the inter-gate dielectric structure, V FB is the determined flat-band voltage, EOT ONO is an equivalent oxide thickness of the inter-gate dielectric structure, V t 0 is a neutral threshold voltage of the flash memory cell, when the floating gate is empty of charge, and α CG is a coupling factor between the control gate and the floating gate.

5. The method according to claim 4 , further comprising determining the neutral threshold voltage (V t 0 ) and the coupling factor (α CG ) from a drain current-control gate potential (I D -V CG ) measurement of the flash memory cell and from a drain current-gate potential (I D -V CG ) measurement of a transistor equivalent to the flash memory cell.

6. The method according to claim 5 , wherein the transistor equivalent to the flash memory cell is comprised of a test memory cell, of identical geometry to the flash memory cell, having a floating gate and a control gate in short-circuit.

7. The method according to claim 2 , wherein the leakage current is determined by fitting the plurality of threshold voltage values (V t i ) with the following relationship:
V t ( t )= A 0 *e −t/τ +A 1 +A 2 *t

where A 0 , A 1 , A 2 are fitting constants, r is a charge trapped-related factor and t is a time during which the control gate bias (V CG OSS ) is applied.

8. A non-transitory machine readable medium comprising a computer program product comprising instructions for implementing the method according to claim 1 , when executed by a processor.

Assignees

• Commissariat Energie Atomique

Inventors

• Coignus Jean
• Dobri Adam
• Jeannot Simon

Classifications

• G11C16/0408 Primary

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title

• G11C16/34 Primary

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G11C2029/5006

  Current · CPC title

• G11C29/50016

  of retention · CPC title