Display driving device, display device and operating method thereof

US9852679B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9852679-B2
Application numberUS-201514837027-A
CountryUS
Kind codeB2
Filing dateAug 27, 2015
Priority dateNov 11, 2014
Publication dateDec 26, 2017
Grant dateDec 26, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device is provided. The display device includes a display panel including a plurality of pixel arrangement areas, a data driving unit including a plurality of source drivers, and a timing controller configured to process data that is input from an external device and configured to generate output data. Each of the plurality of pixel arrangement areas includes a plurality of pixels arranged in areas in which a plurality of gate lines intersect a plurality of data lines. Each of the plurality of source drivers outputs display data to data lines of its corresponding pixels. The timing controller classifies the plurality of pixel arrangement areas based on a distance between the timing controller and each of the plurality of pixel arrangement areas, and transmits the output data to the data driving unit at at least two transmission speeds based on the classification.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: a display panel comprising a plurality of pixel arrangement areas, each of the plurality of arrangement areas comprising a plurality of pixels arranged in areas in which a plurality of gate lines intersect a plurality of data lines; a data driving circuit comprising a plurality of source drivers, each of the plurality of source drivers being configured to output display data to data lines of corresponding pixels; and a timing controller configured to process input data from an external device and configured to generate output data, wherein the display panel is divided into the plurality of pixel arrangement areas based on a distance between the timing controller and each of the plurality of pixel arrangement areas, and wherein based on the divided display panel, the plurality of source drivers are classified into a plurality of driver groups such that one driver group corresponds to a respective pixel arrangement area from among the plurality of pixel arrangement areas; wherein the timing controller is configured to transmit the output data to the data driving circuit such that the output data to a first source driver from among the plurality of source drivers are transmitted at a first transmission speed and the output data to a second source driver from among the plurality of source drivers are transmitted at a second transmission speed different from the first transmission speed. 2. The display device of claim 1 , wherein the number of pixels, in each of the plurality of pixel arrangement areas, changes according to the distance between the timing controller and said each of the plurality of pixel arrangement areas. 3. The display device of claim 1 , further comprising at least two transmission channels configured to transmit the output data from the timing controller to the data driving circuit, wherein a first transmission channel among the at least two transmission channels is configured to transmit the output data at the first transmission speed, and a second transmission channel among the at least two transmission channels is configured to transmit the output data at the second transmission speed. 4. The display device of claim 1 , wherein the timing controller comprises at least two port output terminals configured to transmit the output data to the data driving circuit at different transmission speeds. 5. The display device of claim 1 , wherein the plurality of pixel arrangement areas comprise a first pixel arrangement area and a second pixel arrangement area, and a vertical or horizontal distance between the timing controller and the first pixel arrangement area is shorter than a vertical or horizontal distance between the timing controller and the second pixel arrangement area. 6. The display device of claim 5 , wherein the data driving circuit comprises: a first source driver circuit comprising at least one source driver configured to output a first display data group corresponding to the first pixel arrangement area; and a second source driver circuit comprising at least one source driver configured to output a second display data group corresponding to the second pixel arrangement area, the first source driver circuit and the second source driver circuit being connected to the timing controller through a plurality of transmission channels. 7. The display device of claim 6 , wherein the first transmission speed at which the timing controller transmits a first output data group to the first source driver circuit is higher than the second transmission speed at which the timing controller transmits a second output data group to the second source driver circuit. 8. The display device of claim 7 , wherein the number of pixels of the first pixel arrangement area is greater than the number of pixels of the second pixel arrangement area, and the amount of data of the first output data group is greater than the amount of data of the second output data group. 9. The display device of claim 7 , wherein the data driving circuit comprises an output data buffer configured to receive the output data from the timing controller, and the timing controller is configured to control timing so that the first output data group and the second output data group are simultaneously received by the output data buffer. 10. The display device of claim 7 , wherein the timing controller comprises: a first port output terminal configured to transmit the first output data group at the first transmission speed; and a second port output terminal configured to transmit the second output data group at the second transmission speed. 11. The display device of claim 10 , wherein the number of electrical interconnection lines through which the first port output terminal is connected to the first source driver circuit is less than the number of electrical interconnection lines through which the second port output terminal is connected to the second source driver circuit. 12. A display driving device comprising: a display panel comprising first and second pixel arrangement areas, each of the first and second pixel arrangement areas comprising a plurality of pixels arranged in areas in which a plurality of gate lines intersect a plurality of data lines; a data driving circuit comprising a first source driver circuit configured to output a first display data group to a data line of the first pixel arrangement area, and a second source driver circuit configured to output a second display data group to a data line of the second pixel arrangement area; a timing controller configured to array input data and configured to transmit output data to the data driving circuit at at least two preset transmission speeds corresponding to respective arrangement area from among the first and second pixel arrangement areas, the timing controller being configured to generate timing control signals; a gate driving circuit configured to receive one of the timing control signals and configured to drive the plurality of gate lines of the display panel; and a voltage generating circuit configured to generate voltages for driving the display panel, wherein the display panel is divided into the first pixel arrangement area and the second pixel arrangement area and based on the divided display panel, the first source driver circuit outputs the first display data group to the data line of the first pixel arrangement area and the second source driver circuit outputs the second display data group to the data line of the second pixel arrangement area, and wherein the timing controller transmits the output data at said at least two transmission speeds which are different from each other based on the divided display panel. 13. The display driving device of claim 12 , wherein a printed circuit board (PCB) with the first source driver circuit formed thereon is connected to a PCB with the second source driver circuit formed thereon through a bridge cable. 14. The display driving device of claim 12 , wherein a vertical or horizontal distance from the timing controller to the first source driver circuit is shorter than a vertical or horizontal distance from the timing controller to the second source driver circuit. 15. The display driving device of claim 14 , wherein the amount of data of the first display data group is greater than the amount of data of the second display data group. 16. The display driving device of claim 14 , wherein the first source driver circuit comprises at least one first source driver configured to support a first transmission speed, the second source driver circuit

Assignees

Inventors

Classifications

  • Parallel handling of streams of display data · CPC title

  • Driving circuits for producing the waveforms applied to the driving electrodes · CPC title

  • G09G3/2092Primary

    Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title

  • using sub-pixels · CPC title

  • by domain size control (G09G3/3637 takes precedence) · CPC title

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What does patent US9852679B2 cover?
A display device is provided. The display device includes a display panel including a plurality of pixel arrangement areas, a data driving unit including a plurality of source drivers, and a timing controller configured to process data that is input from an external device and configured to generate output data. Each of the plurality of pixel arrangement areas includes a plurality of pixels arr…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/2092. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 26 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).