Standard cell library and methods of using the same

Patent metadata

Field	Value
Publication number	US-9852252-B2
Application number	US-201514801239-A
Country	US
Kind code	B2
Filing date	Jul 16, 2015
Priority date	Aug 22, 2014
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.

First claim

What is claimed is:

1. A method of operating a computing device for designing an integrated circuit (IC) using a standard cell library comprising information regarding a plurality of standard cells, the method comprising:
receiving input data at the computing device defining the IC comprising at least one of the plurality of standard cells, the at least one of the plurality of standard cells comprising a pin which comprises first and second regions perpendicular to a stack direction;
accessing a non-transitory computer readable storage medium storing the standard cell library that is coupled to the computing device, the standard cell library further comprising marker information corresponding to the second region of the pin; and
placing and routing, by a processor of the computing device, the at least one of the plurality of standard cells included in the IC by disposing a via in the second region of the pin rather than the first region of the pin based on the marker information,
wherein, if the via is disposed in the second region of the pin, a resistance value of the via is smaller than if the via is placed in the first region of the pin, and
wherein the second region is spaced apart from at least a part of a boundary of the pin.

2. The method of claim 1 , wherein the placing and routing the at least one of the plurality of standard cells comprises:
placing first and second patterns respectively on first and second layers to be formed after forming the pin during a semiconductor process,
wherein the via connects the first and second patterns, and
wherein the placing of the first and second patterns comprises disposing the via in a region spaced apart from the boundary of the first or second pattern by more than a previously determined distance in at least two directions from among four directions perpendicular to the stack direction.

3. The method of claim 1 , wherein the placing and routing the at least one of the plurality of standard cells further comprises disposing the via according to a grid defined in a layout of the IC.

4. The method of claim 1 , further comprising generating output data defining the IC comprising the placed and routed standard cells.

5. The method of claim 4 , further comprising manufacturing the IC using the generated output data defining the IC.

6. The method of claim 1 , wherein the second region is spaced apart from at least a part of boundary of the pin by a first distance, and
wherein the first region is within the pin and spaced apart from at least a part of the boundary of the pin by a second distance, less than the first distance.

7. A method of operating a computing device for designing an integrated circuit (IC) using a standard cell library comprising information regarding a plurality of standard cells,
the method comprising:
receiving input data at the computing device defining the IC comprising at least one of the plurality of standard cells, the at least one of the plurality of standard cells comprising a pin which comprises first and second regions perpendicular to a stack direction;
accessing a non-transitory computer readable storage medium storing the standard cell library that is coupled to the computing device, the standard cell library further comprising marker information corresponding to the second region of the pin; and
placing and routing, by a processor of the computing device, the at least one of the plurality of standard cells included in the IC by disposing a via in the second region of the pin rather than the first region of the pin based on the marker information,
wherein, if the via is disposed in the second region of the pin, a resistance value of the via is smaller than if the via is placed in the first region of the pin, and
wherein the placing and routing the at least one of the plurality of standard cells comprises analyzing a timing characteristic of the IC based on the resistance value of the via disposed in the second region.

8. The method of claim 7 , wherein when the via is disposed in the second region of the pin, the second region is defined in such a manner that the via is spaced apart from a boundary of the pin in first and second directions perpendicular to each other by at least first and second distances respectively or is spaced apart from the boundary of the pin in the first direction and a third direction that are opposite to each other by at least the first distance.

9. The method of claim 7 , wherein the placing and routing the at least one of the plurality of standard cells comprises:
placing first and second patterns respectively on first and second layers to be formed after forming the pin during a semiconductor process,
wherein the via connects the first and second patterns, and
wherein the placing of the first and second patterns comprises disposing the via in a region spaced apart from a boundary of the first or second pattern by more than a previously determined distance in at least two directions from among four directions perpendicular to the stack direction.

10. The method of claim 7 , wherein the placing and routing the at least one of the plurality of standard cells further comprises disposing the via according to a grid defined in a layout of the IC.

11. The method of claim 7 , further comprising generating output data defining the IC comprising the placed and routed standard cells.

12. The method of claim 11 , further comprising manufacturing the IC using the generated output data defining the IC.

13. A method of operating a computing device using for designing an integrated circuit (IC) a standard cell library comprising information regarding a plurality of standard cells, the method comprising:
receiving input data at the computing device defining the IC comprising at least one of the plurality of standard cells, the at least one of the plurality of standard cell comprising a pin which comprises first and second regions perpendicular to a stack direction;
accessing a non-transitory computer readable storage medium storing the standard cell library that is coupled to the computing device, the standard cell library further comprising marker information corresponding to the second region of the pin; and
placing and routing, by a processor of the computing device, the at least one of the plurality of standard cells included in the IC by disposing a via in the second region of the pin rather than the first region of the pin based on the marker information,
wherein, if the via is disposed in the second region of the pin, a resistance value of the via is smaller than if the via is placed in the first region of the pin, and
wherein the placing and routing the at least one of the plurality of standard cells comprises selecting a first standard cell connected to a critical path of the IC for disposing the via in the second region rather than other standard cells included in the IC not connected to the critical path of the IC.

14. The method of claim 13 , wherein when the via is disposed in the second region of the pin, the second region is defined in such a manner that the via is spaced apart from a boundary of the pin in first and second directions perpendicular to each other by at least first and second distances respectively or is spaced apart from the boundary of the pin in the first direction and a third direction that are opposite to each other by at least the first distance.

15. The method of claim 13 , wherein the placing and routing the at least one of the plurality of standard cells comprises:
placing first and second patterns respectively on first and second layers to be formed after forming the pi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sang-Hoon
• Song Tae-Joong
• Park Jae-Ho
• Yang Gi-Young
• Kim Jin-Tae
• Won Hyo-Sig

Classifications

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5031

  Physics · mapped topic