Manipulating parameterized cell devices in a custom layout design

Patent metadata

Field	Value
Publication number	US-9852251-B2
Application number	US-201414203300-A
Country	US
Kind code	B2
Filing date	Mar 10, 2014
Priority date	Jun 11, 2010
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit.

First claim

What is claimed is:

1. A computer-implemented method for generating a layout of a circuit, the method comprising:
invoking the computer to receive a parameterized cell layout having a plurality of attributes;
receiving data associated with an attribute of the parameterized cell layout via the computer;
converting the parameterized cell layout, via the computer, to an associated symbolic cell layout in accordance with the received data, said symbolic cell layout being an abstract view of the parameterized cell layout;
displaying the symbolic cell layout; and
generating a second layout of the parameterized cell from the symbolic cell layout, said layout to be manufactured.

2. The computer-implemented method of claim 1 , wherein the attribute is selected from a group consisting of a finger number parameter, a width parameter, a length parameter, a left most OD extension parameter, and a right most OD extension parameter.

3. The computer-implemented method of claim 1 , wherein the data is associated with the abutment of the parameterized cell.

4. The computer-implemented method of claim 1 , wherein the data causes a finger number parameter of the parameterized cell to change.

5. The computer-implemented method of claim 1 , wherein the data causes a change in the alignment of the parameterized cell by determining a difference between a pitch of two elements associated with the parameterized cell and applying the difference to an extension parameter, wherein the generated second layout includes an adjusted aspect of one of the two elements.

6. The computer-implemented method of claim 1 wherein the data is associated with a width parameter of the parameterized cell.

7. The computer-implemented method of claim 1 wherein the data is associated with a channel width parameter of the parameterized cell.

8. The computer-implemented method of claim 1 wherein the data is associated with a length parameter of the parameterized cell.

9. The computer-implemented method of claim 1 wherein the data is associated with a left most OD extension parameter of the parameterized cell.

10. The computer-implemented method of claim 1 wherein the data is associated with a right most OD extension parameter of the parameterized cell.

11. The computer-implemented method of claim 1 wherein the data is associated with an alignment of the parameterized cell.

12. A computer system configured to generate a layout of an integrated circuit, the apparatus comprising:
a processor;
a video display;
a non-transitory computer readable storage medium comprising instructions which when executed by the processor cause the processor to:
invoke the computer system to receive a parameterized cell layout having a plurality of attributes;
receive data associated with an attribute of the parameterized cell layout;
convert the parameterized cell layout to an associated symbolic cell layout in accordance with the received data, said symbolic cell layout being an abstract view of the parameterized cell layout;
display the symbolic cell layout; and
generate a second layout of the parameterized cell from the associated symbolic cell layout, said layout to be manufactured.

13. The computer system of claim 12 , wherein the instructions further cause the processor to select from a group consisting of a finger number parameter, a width parameter, a length parameter, a left most OD extension parameter, and right most OD extension parameter.

14. The computer system of claim 12 , wherein the instructions further cause the processor to change a finger number parameter of the parameterized cell in accordance with the data.

15. The computer system of claim 12 , wherein the instructions further cause the processor to determine a difference between a pitch of two elements associated with the parameterized cell in accordance with the data and apply the difference to an extension parameter, wherein the generated second layout adjusted aspect of one of the two elements.

16. The computer system of claim 12 wherein the data is associated with a width parameter of the parameterized cell.

17. The computer system of claim 12 wherein the data is associated with a channel width parameter of the parameterized cell.

18. The computer system of claim 12 wherein the data is associated with a length parameter of the parameterized cell.

19. The computer system of claim 12 wherein the data is associated with a left most OD extension parameter of the parameterized cell.

20. The computer system of claim 12 wherein the data is associated with a right most OD extension parameter of the parameterized cell.

21. The computer system of claim 12 wherein the data is associated with an alignment of the parameterized cell.

Assignees

• Synopsys Inc
• Synopsys Taiwan Co Ltd

Inventors

• Lu Hsiao-Tzu
• Mcdonald Duncan Robert
• Yuan Chih-Wei
• Kang Wen-Lung

Classifications

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/5068

  Physics · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title