Apparatus for controlling inverse fast fourier transform input in long term evolution system

Patent metadata

Field	Value
Publication number	US-9852110-B2
Application number	US-201514982846-A
Country	US
Kind code	B2
Filing date	Dec 29, 2015
Priority date	Jan 21, 2015
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Disclosed is an apparatus for controlling an IFFT input in a LTE system. The apparatus includes: a first multiplexer configured to select a portion of data applied to a first stage of a Fast Fourier Transform (FFT) structure according to a predefined condition from among input data, and assign the selected data to a memory of the first stage; a butterfly operator configured to receive the portion of data selected by the first multiplexer and perform a butterfly operation for the first stage of the FFT structure using the received data; a multiplier configured to output a value obtained by multiplying a result value output from the butterfly operator and a predetermined value together; and a second multiplexer configured to receive a value output via the multiplier, and remaining data not selected by the first multiplexer to output to a second stage of the FFT structure.

First claim

What is claimed is:

1. An apparatus for controlling an Inverse Fast Fourier Transform (IFFT) input in a wireless communication system, the apparatus comprising:
a first multiplexer configured to select a portion of data applied to a first stage of a Fast Fourier Transform (FFT) structure according to a predefined condition from among input data, and assign remaining data following the portion of the data to a memory of a second stage of the FFT structure, wherein the remaining data is data which is not selected by the first multiplexer;
a butterfly operator configured to receive the portion of the data selected by the first multiplexer and perform a butterfly operation for the first stage of the FFT structure using the received data;
a multiplier configured to output a value obtained by multiplying a result value output from the butterfly operator and a predetermined value together; and
a second multiplexer configured to receive a value output via the multiplier and the remaining data to output to the second stage,
wherein the portion of the data has a size of A-B/2 and the remaining data has a size B/2, wherein A represent a size of the symbol data, B represents a size of null data, and 2A represent a size of a total symbol data.

2. The apparatus of claim 1 , wherein the first multiplexer selects the portion of the data after a specified clock, and selects the remaining data to assign to the memory of the second stage.

3. The apparatus of claim 1 , wherein the butterfly operator stores the portion of the data in a memory of the first stage through the first multiplexer, and performs an addition operation and a subtraction operation with respect to data inputted after specified clock and data previously stored in the memory of the first stage.

4. The apparatus of claim 1 , wherein the butterfly operator stores a subtraction value in a memory of the first stage as a result of the butterfly operation, and outputs an addition value to the multiplier.

5. The apparatus of claim 1 , wherein a memory of the first stage stores a subtraction value output from the butterfly operator, and feedbacks the stored value to the butterfly operator after specified clock.

6. The apparatus of claim 5 , wherein the subtraction value stored in the memory of the first stage is output to the second stage after a certain clock.

7. The apparatus of claim 5 , wherein the multiplier performs multiplying operation with respect to an operation value output from the butterfly operator and a predetermined complex value.

8. The apparatus of claim 5 , wherein the butterfly operator is implemented by a RADIX-2 typed single path feedback structure, and performs a RADIX-2 butterfly operation with respect to data input from the first multiplexer.

9. A method for controlling an Inverse Fast Fourier Transform (IFFT) input in a wireless communication system, the method comprising:
sending symbol data of which a size is A-B/2 to a first stage of a IFFT structure and then, sending remaining symbol data of B/2 to the first stage, wherein A represent a size of the symbol data, B represents a size of null data, and 2A represent a size of a total symbol data input to the IFFT structure; and
forwarding the symbol data of A-B/2 to a butterfly operator according to a predefined condition, and assigning the remaining symbol data to a memory of a second stage of the FFT structure.

10. The method of claim 9 , further comprising:
receiving the forwarded data and performing a butterfly operation for the first stage using the forwarded data;
outputting a value obtained by multiplying a result value output from the butterfly operator and a predetermined value together; and
receiving a value output via the multiplier and the remaining data which is assigned by a first multiplexer in the first stage to output to the second stage.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Jang In Gul

Classifications

• G06F17/142 Primary

  Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm · CPC title

• H04L27/00

  Modulated-carrier systems · CPC title

• H04L27/263 Primary

  modification of IFFT/IDFT modulator for performance improvement · CPC title

• H04L27/2634

  Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation · CPC title

• H04L27/26

  Systems using multi-frequency codes (H04L27/32 takes precedence) · CPC title