Method and device for serial data transmission having a flexible message size and a variable bit length

Patent metadata

Field	Value
Publication number	US-9852106-B2
Application number	US-201214129611-A
Country	US
Kind code	B2
Filing date	Jun 26, 2012
Priority date	Jun 29, 2011
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A method for serial data transfer in a bus system having at least two bus subscribers that exchange messages via the bus, the transmitted messages having a logical structure according to CAN standard ISO 11898-1, the logical structure encompassing a start of frame bit, arbitration field, control field, data field, CRC field, acknowledge field, and end of frame sequence, the control field encompassing a data length code that contains an information item regarding the length of the data field. The method is characterized in that when a first marker (EDL) is present, the control field of the messages, divergently from ISO 11898-1, encompasses more than six bits; the first marker (EDL) being implemented by way of a recessive bit in the control field, and when the first marker is present, the recessive bit of the first marker (EDL) being followed, in all data messages, by at least one dominant bit.

First claim

What is claimed is:

1. A method for serial data transfer in a bus system having at least two bus subscribers that exchange messages via the bus, the method comprising:
exchanging messages via the bus, transmitted ones of the messages having a logical structure in accordance with the CAN standard ISO 11898-1, the logical structure encompassing a start of frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field, and an end of frame sequence, the control field encompassing a data length code that contains an information item regarding the length of the data field;
providing, when a first marker (EDL) is present, that the control field of the messages, divergently from the CAN standard ISO 11898-1, encompasses more than six bits;
implementing the first marker (EDL) by a recessive bit in the control field; and
providing that, when the first marker is present, the recessive bit of the first marker (EDL) is followed, in all data messages, by at least one dominant bit.

2. The method of claim 1 , wherein a recessive-dominant edge that is produced by the dominant bit following the recessive bit of the first marker (EDL) in all data messages is utilized to improve synchronization between the bus subscribers.

3. The method of claim 1 , wherein a hard synchronization is carried out by the bus subscribers at a recessive-dominant edge that is produced by the dominant bit following the recessive bit of the first marker (EDL) in all data messages.

4. The method of claim 1 , wherein when the first marker (EDL) is present, the data field of the messages, divergently from the CAN standard ISO 11898-1, can encompass more than eight bytes, values of four bits of the data length code being interpreted at least in part divergently from the CAN standard ISO 11898-1 to establish a size of the data field.

5. The method of claim 1 , wherein when a second marker (BRS) is present, a bit length for at least one predefined or predefinable region within the messages assumes a value that is shortened with respect to the bit length used before the second marker was present, the region beginning at the earliest with the second marker and ending at the latest with a CRC delimiter, the second marker (BRS) occurring only when the first marker (EDL) is present, and occurring in the control field of the messages which, divergently from the CAN standard ISO 11898-1, encompasses more than six bits.

6. The method of claim 5 , wherein the second marker (BRS) is implemented by another recessive bit in the control field which is transferred later in time than the bit of the first marker (EDL).

7. The method of claim 6 , wherein when the second marker is present, the recessive bit of the second marker (BRS) is separated from the recessive bit of the first marker (EDL) by at least one dominant bit.

8. The method of claim 1 , wherein the first marker (EDL) is evaluated in the bus subscribers and, as a function of the first marker, a receiving process is adapted to a size of the control field and/or of the data field and/or of subsequent constituents of the messages.

9. The method of claim 5 , wherein the second marker (BRS) is evaluated in the bus subscribers when the first marker is present, and as a function of the value of the second marker, a receiving process is adapted to different values of the bit length within a message.

10. The method of claim 5 , wherein at least two different values of a time-related bit length within a message are realized by using at least two different scaling factors to adjust a bus time unit during operation relative to a shortest time unit or to an oscillator clock.

11. The method of claim 1 , wherein when a further marker is present, the CRC field of the messages has a number of bits divergent from the CAN standard ISO 11898-1, and/or at least one generator polynomial divergent from the CAN standard ISO 11898-1 is used, where the further marker can match the first marker (EDL).

12. The method of claim 11 , wherein a value of the further marker is ascertained in the bus subscribers, and a receiving process is adapted to a size of the CRC field depending on the value of the further marker and/or on content of the data length code.

13. The method of claim 11 , wherein at a beginning of a message, calculation of at least two CRC checksums using different generator polynomials is started concurrently, and as a function of a value of the further marker, a decision is made as to which result from one of the concurrently started CRC calculations is used.

14. An apparatus for serial data transfer in a bus system having at least two bus subscribers that exchange messages via the bus, comprising:
an exchange arrangement to exchange messages via the bus, transmitted ones of the messages having a logical structure in accordance with the CAN standard ISO 11898-1, the logical structure encompassing a start of frame bit, an arbitration field, a control field, a data field, a CRC field, an acknowledge field, and an end of frame sequence, the control field encompassing a data length code that contains an information item regarding the length of the data field;
a control arrangement to provide, when a first marker (EDL) is present, that the control field of the messages, divergently from the CAN standard ISO 11898-1, encompasses more than six bits, to implement the first marker (EDL) by a recessive bit in the control field, and to provide that, when the first marker is present, the recessive bit of the first marker (EDL) is followed, in all data messages, by at least one dominant bit.

15. The apparatus of claim 14 , wherein a recessive-dominant edge that is produced by the dominant bit following the recessive bit of the first marker (EDL) in all data messages is utilized in the apparatus to improve synchronization between the bus sub scribers.

16. The apparatus of claim 14 , wherein a hard synchronization of the bus subscribers is carried out by the apparatus at a recessive-dominant edge that is produced by the dominant bit following the recessive bit of the first marker (EDL) in all data messages.

17. The apparatus of claim 14 , wherein when the first marker (EDL) is present, the data field of the messages, divergently from the CAN standard ISO 11898-1, can encompass more than eight bytes, values of four bits of the data length code being interpreted at least in part divergently from the CAN standard ISO 11898-1 in order to establish a size of the data field.

18. The apparatus of claim 14 , wherein when a second marker (BRS) is present, a bit length for at least one predefined or predefinable region within the messages assumes a value that is shortened with respect to the bit length used before the second marker was present, the region beginning at the earliest with the second marker and ending at the latest with a CRC delimiter, the second marker (BRS) occurring only when the first marker (EDL) is present, and occurring in the control field of the messages which, divergently from the CAN standard ISO 11898-1, encompasses more than six bits.

19. The apparatus of claim 14 , wherein a second marker (BRS) is implemented by another recessive bit in the control field which is transferred later in time than the bit of the first marker (EDL).

20. A method for serial data transfer, during normal operation of a motor vehicle to transfer data between at least two control units of the motor vehicle that are connected via a data bus in a bus system having at least two bus subscribers that exchange messages via the bus, the method comp

Assignees

• Hartwich Florian
• Horst Christian
• Bosch Gmbh Robert

Inventors

• Hartwich Florian
• Horst Christian

Classifications

• H04L2012/40215

  Controller Area Network CAN · CPC title

• H04L2001/0094

  Bus · CPC title

• H04L47/36

  by determining packet size, e.g. maximum transfer unit [MTU] · CPC title

• H04L12/40169

  Flexible bus arrangements (arrangements for maintenance or administration involving management of faults; events, alarms H04L41/06; automatic restoration of network faults H04L41/0654) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title