Memory device and operating method of memory device

US9852061B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9852061-B2
Application numberUS-35827809-A
CountryUS
Kind codeB2
Filing dateJan 23, 2009
Priority dateOct 2, 2008
Publication dateDec 26, 2017
Grant dateDec 26, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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A memory device may include a non-volatile memory and non-volatile RAM. The non-volatile memory may include a data block and a metadata block. Metadata information with respect to the data block may be included in the metadata block. A portion of metadata with respect to the data block or the metadata with respect to the metadata block may be stored in the non-volatile RAM.

First claim

Opening claim text (preview).

What is claimed is: 1. A memory device, comprising: a processor configured to verify that a write command of a non-volatile memory is a sequential write in response to a size of data of the write command being greater than or equal to a threshold, and verify that the write command is a random write in response to the size of the data of the write command being less than the threshold; the non-volatile memory including data blocks and a metadata block and configured to store first metadata corresponding to the data blocks in the metadata block; and a non-volatile RAM configured to read and write in byte units or word units, and store second metadata, wherein the non-volatile RAM is configured to store data corresponding to a write command and store map information of the stored data, in response to the write command of the non-volatile memory being verified to be a random write. 2. The memory device of claim 1 , wherein the second metadata includes an erase count of each of the data blocks. 3. The memory device of claim 1 , wherein the second metadata includes state information corresponding to each of pages included in each of the respective data blocks. 4. The memory device of claim 1 , wherein the second metadata includes an erase count of the metadata block. 5. The memory device of claim 1 , wherein the second metadata includes state information of each of the pages included in the metadata block. 6. The memory device of claim 1 , wherein: the second metadata includes a mapping relation between the logical block address and physical address of a data page stored in the data blocks; and the first metadata includes a mapping relation between the logical page address and a physical page address in the logical block address of the data page stored in the data blocks. 7. The memory device of claim 1 , wherein the RAM is configured to: select eviction data from among the stored data based on the map information in response to a size of available space being less than a threshold; and program one of the data blocks of the non-volatile memory with the eviction data. 8. The memory device of claim 7 , wherein the non-volatile RAM is configured to: program the one of the data blocks with the eviction data; and update the map information. 9. The memory device of claim 1 , wherein the non-volatile RAM is configured to output stored data as data corresponding to a read command; in response to data of the read command of the non-volatile memory existing in the non-volatile RAM. 10. A method of operating a memory device including a non-volatile memory and a non-volatile RAM, the method comprising: verifying that a write command of the non-volatile memory is a sequential write in response to a size of data of the write command being greater than or equal to a threshold; verifying that the write command is a random write in response to the size of the data of the write command being less than the threshold; storing data corresponding to the write command and storing map information of the stored data in the non-volatile RAM in response to the write command of the non-volatile memory being verified to be the random write; and programming data corresponding to the write command in the non-volatile memory in response to the write command being verified to be the sequential write. 11. The method of claim 10 , further comprising: verifying whether a size of available space of the non-volatile RAM is less than the threshold; selecting eviction data from among data stored in the non-volatile RAM in response to the size of the available space being verified to be less than the threshold; and programming the eviction data to the non-volatile memory. 12. The method of claim 10 , further comprising: verifying whether data corresponding to a read command with respect to the non-volatile memory exists in the non-volatile RAM; reading data corresponding to the read command from the non-volatile RAM in response to the data corresponding to the read command being verified to exist in the non-volatile RAM; and transmitting the data read from the non-volatile RAM to a host or a controller. 13. A method of operating a memory device including a non-volatile memory and a non-volatile RAM, the method comprising: converting a logical block address of an access command of the non-volatile memory into a physical address based on map information stored in the non-volatile RAM; accessing page map information stored in a metadata area of the non-volatile memory based on the physical address; converting a logical page address of the access command into a physical page address based on the accessed page map information; accessing data stored in a data area of the non-volatile memory based on the physical page address; and assigning the access command to any one of channels of the non-volatile memory based on a remainder after dividing the logical block address or the logical page address of the access command by a number of the channels, wherein a value of the remainder determines the assigning of the access command to a specified channel. 14. A non-transitory computer-readable storage medium storing a program to operate a memory device including a non-volatile memory and a non-volatile RAM, comprising instructions to cause a computer to: verify that a write command of the non-volatile memory is a sequential write in response to a size of data of the write command being greater than or equal to a threshold; verify that the write command is a random write in response to the size of the data of the write command being less than the threshold; store data corresponding to the write command and store map information of the stored data in the non-volatile RAM in response to the write command of the non-volatile memory being verified to be the random write; and program data corresponding to the write command in the non-volatile memory in response to the write command being the sequential write.

Assignees

Inventors

Classifications

  • in block erasable memory, e.g. flash memory · CPC title

  • Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

  • Cleaning, compaction, garbage collection, erase control · CPC title

  • Logical to physical mapping or translation of blocks or pages · CPC title

  • management of metadata or control data · CPC title

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What does patent US9852061B2 cover?
A memory device may include a non-volatile memory and non-volatile RAM. The non-volatile memory may include a data block and a metadata block. Metadata information with respect to the data block may be included in the metadata block. A portion of metadata with respect to the data block or the metadata with respect to the metadata block may be stored in the non-volatile RAM.
Who is the assignee on this patent?
Lee Jae Don, Lee Choong Hun, Choi Gyu Sang, and 2 more
What technology area does this patent fall under?
Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 26 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).