Concurrent memory operations for read operation preemption

Patent metadata

Field	Value
Publication number	US-9851905-B1
Application number	US-201615280898-A
Country	US
Kind code	B1
Filing date	Sep 29, 2016
Priority date	Sep 29, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A non-volatile memory interface employs concurrent memory operations for read operation preemption and includes transaction control logic configured to resume a suspended write operation concurrently with at least a portion of the transfer of read data from a non-volatile memory for a read operation which preempted the write operation. Memory control logic of the memory interface is configured to issue to the write operation suspend logic, a write operation resume command. The transaction control logic may be further configured to automatically suspend performing of a write operation in response to receipt of a read command. The transaction control logic may also be configured to automatically resume a previously suspended write operation in response to completion of a preemptive read operation by the memory.

First claim

What is claimed is:

1. An apparatus for a non-volatile memory, comprising:
a non-volatile memory interface including:
write operation logic configured to receive a write command and to perform a write operation in response to a received write command;
write operation suspend logic configured to receive a command, and to suspend a write operation in response to the command received by the write operation suspend logic;
read operation logic configured to receive a read command and to perform a read operation in response to a received read command; and
data transfer logic configured to transfer read data of the read operation from the memory;
wherein the write operation suspend logic is further configured to resume a suspended write operation concurrently with at least a portion of the transfer of read data from the memory.

2. The apparatus of claim 1 wherein the non-volatile memory interface includes a controller having memory command issuance logic configured to issue a write operation suspend command to the write operation suspend logic of the non-volatile memory interface and wherein the command received by the write operation suspend logic is the write operation suspend command to cause the write operation suspend logic to suspend a write operation in response to the write operation suspend command received by the write operation suspend logic.

3. The apparatus of claim 2 wherein the memory command issuance logic is further configured to issue to the read operation logic a read command in association with issuance of a write operation suspend command.

4. The apparatus of claim 3 wherein the controller includes the data transfer logic which is further configured to, in response to completion of a read operation, to transfer read data of the completed read operation from the memory, and wherein the memory command issuance logic is further configured to issue to the write operation suspend logic a write operation resume command to initiate resumption of a previously suspended write operation command so that the data transfer logic is configured to transfer at least a portion of the read data from the memory concurrently with resumption of a write operation in response to the write operation resume command issued by the memory command issuance logic.

5. The apparatus of claim 1 wherein the command received by the write operation suspend logic is a read command, wherein the write operation suspend logic is configured to automatically suspend performing of a write operation in response to receipt of a read command by the write operation suspend logic.

6. The apparatus of claim 5 wherein the non-volatile memory interface includes a controller having memory command issuance logic configured to issue a read command, wherein the write operation suspend logic is further configured to automatically resume a previously suspended write operation in response to completion of a read operation by the read operation logic, and wherein the controller includes the data transfer logic which is further configured to, in response to completion of a read operation, to transfer read data of the completed read operation from the memory, so that the data transfer logic is configured to transfer at least a portion of the read data from the memory concurrently with resumption of a write operation in response to completion of a read operation.

7. A method, comprising:
performing by a memory transaction control logic, a write operation in a non-volatile memory in response to a write command received by the memory transaction control logic;
receiving by the memory transaction control logic, a command while performing the write operation;
in response to the received command, suspending by the memory transaction control logic, the performing of the write operation;
performing by the memory transaction control logic, a read operation while the write operation is suspended;
transferring by a controller, read data of the read operation from the memory; and
concurrently with at least a portion of the read data transferring from the memory, resuming by the memory transaction control logic, the performing of the write operation.

8. The method of claim 7 further comprising a controller issuing a write operation suspend command to the memory transaction control logic wherein the command received by the memory transaction control logic while performing the write operation is the write operation suspend command issued by the controller so that in response to the received write operation suspend command, the memory transaction control logic suspends the performing of the write operation.

9. The method of claim 7 further comprising the controller issuing to the memory transaction control logic a read operation in association with the write operation suspend command.

10. The method of claim 9 further comprising in response to completion by the memory transaction control logic of the performing of the read operation issued by the controller, the controller issuing to the memory transaction control logic a write operation resume command and initiating the transferring of read data of the read operation from the memory so that concurrently with at least a portion of the read data transferring from the memory, the memory transaction control logic initiates a resumption of the write operation in response to the write operation resume command issued by the controller.

11. The method of claim 7 wherein the command received by the memory transaction control logic while performing the write operation is a read command, wherein the memory transaction control logic automatically suspends the performing of the write operation in response to receipt of the read command by the memory transaction control logic.

12. The method of claim 7 further comprising:
issuing by the controller to the memory transaction control logic, a read command for the read operation;
in response to completion by the memory transaction control logic of the performing of the read operation for the read command issued by the controller, the memory transaction control logic automatically resuming the write operation; and
in response to completion by the memory transaction control logic of the performing of the read operation for the read command issued by the controller, the controller transferring read data of the read operation from the memory so that concurrently with at least a portion of the read data transferring from the memory, the memory transaction control logic resumes the write operation.

13. A system, comprising:
a central processing unit;
a non-volatile memory including an array of bit cells; and
a non-volatile memory interface for the central processing unit and the array of bit cells;
wherein the central processing unit is configured to generate and transmit to the non-volatile memory interface, a memory transaction request and a system address at which the memory transaction is to take place;
and wherein the non-volatile memory interface includes:
write operation logic configured to receive a write command and to perform a write operation in response to a received write command;
write operation suspend logic configured to receive a command, and to suspend a write operation in response to the command received by the write operation suspend logic;
read operation logic configured to receive a read command and to perform a read operation in response to a received read command; and
data transfer logic configured to transfer read data of the read operation from the memory;
wherein the write operation suspend logic is further configured to resume a suspended write operation concurrently with at least a po

Assignees

• Intel Corp

Inventors

• Ramalingam Anand S
• Kalavade Pranav
• Madraswala Aliasgar S

Classifications

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title