Dynamic power measurement and estimation to improve memory subsystem power performance

Patent metadata

Field	Value
Publication number	US-9851771-B2
Application number	US-201314142808-A
Country	US
Kind code	B2
Filing date	Dec 28, 2013
Priority date	Dec 28, 2013
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

Dynamic monitoring of current draw by a memory device or memory subsystem can enable a power management system to adjust a memory access performance parameter based on monitored power usage. The system can generate a power usage characterization for the memory device and/or memory subsystem based on monitoring current draw for a known pattern, and then subsequently use the power usage characterization to determine how to adjust the memory access performance parameter.

First claim

What is claimed is:

1. A method comprising:
monitoring a current draw from a memory device in response to the memory device receiving one or more known traffic patterns, including monitoring the current draw based on memory access from different sources in a processing system that includes the memory device, the different sources including a central processor and a graphics processor;
wherein monitoring comprises receiving sensor input from current sensors in a voltage regulator that provides power to the memory device,
generating a power usage characterization for the memory device based on the monitored current draw for the known traffic patterns, the power usage characterization identifying power usage with respect to the different sources of memory access; based on the power usage characterization, generating a power estimate to identify estimated power usage with respect to the different sources of memory access including for the central processor and the graphics processor; and
performing load balancing among the different sources of memory access in the processing system based on a difference detected between the power estimate and actual power usage of the memory device, the load balancing including: in response to detecting the current draw from the memory device is higher than or equal to a threshold, lowering bandwidth for memory accesses from the central processor or the graphics processor based on the power usage characterization that identifies power usage with respect to the different sources of memory access.

2. The method of claim 1 , wherein the memory device is part of a memory subsystem, and wherein the monitoring, the generating, and the adjusting are performed relative to the memory subsystem.

3. The method of claim 1 , wherein the memory device is part of a system-on-a-chip (SOC) including the different sources of memory access, and wherein generating the power usage characterization for the memory device comprises generating the power usage characterization for multiple different traffic patterns including traffic from the different sources of memory access of the SOC.

4. The method of claim 3 , wherein load balancing among the different sources of memory access is based on different power usage characterizations for the different traffic patterns including the memory access traffic to the memory device from the different sources of memory access of the SOC.

5. The method of claim 1 , further comprising: monitoring current draw for the memory device for runtime memory access traffic; and throttling bandwidth of the memory access traffic sent to the memory device based on monitoring the current draw for the runtime memory access traffic.

6. The method of claim 1 , further comprising: monitoring current draw for the memory device for runtime memory access traffic; and adjusting one or more of an operating voltage or an operating frequency of a memory access interface based on monitoring the current draw for the runtime memory access traffic.

7. The method of claim 1 , wherein: monitoring the current draw from the memory device is based on memory access from the different sources including a central processor and a graphics processor; and wherein load balancing comprises load balancing among the different sources, including the central processor and the graphics processor.

8. A power management system, comprising:
a current sensor to generate current usage information for a memory device based on a measurement of current for the memory device in active operation and performing monitoring of power usage pattern of known traffic,
wherein monitoring comprises receiving sensor input from current sensors in a voltage regulator that provides power to the memory device;

and
a processor device configured to execute a power manager, the processor device to control a memory controller coupled to provide a memory access interface to the memory device, the power manager to receive the current usage information from the current sensor, determine to load balance among different sources of memory access in the processing system based on the current usage information received from the current sensor, a power usage characterization for the memory device, and
a power estimate to identify estimated power usage with respect to the different sources of memory access, including for the central processor and the graphics processor, and
perform load balancing among the different sources of memory access in the processing system based on a difference detected between the current usage information and the power estimate, including: in response to detection that the current for the memory device is higher than or equal to a threshold, to lower bandwidth for memory accesses from the central processor or the graphics processor based on the power usage characterization that identifies power usage with respect to the different sources of memory access.

9. The power management system of claim 8 , wherein the current sensor comprises a current sensor in a power management integrated circuit of a voltage regulator coupled to provide power to the memory device.

10. The power management system of claim 8 , wherein the memory device is part of a system-on-a-chip (SOC) having multiple different sources of memory access, and wherein the power manager is further to generate the power usage characterization for multiple different traffic patterns including memory access traffic from the different sources of memory access of the SOC.

11. The power management system of claim 10 , wherein the power manager is to load balance among the different sources of memory access based on different power usage characterizations for the different traffic patterns.

12. The power management system of claim 8 , wherein the power manager is to further: monitor current draw for the memory device for runtime memory access traffic; and wherein the power manager is to throttle bandwidth of the memory access traffic sent to the memory device based on monitoring the current draw for the runtime memory access traffic.

13. The power management system of claim 8 , wherein the power manager is to further: monitor current draw for the memory device for runtime memory access traffic; and adjust one or more of an operating voltage or an operating frequency of a memory access interface based on monitoring the current draw for the runtime memory access traffic.

14. The power management system of claim 8 , wherein: the current usage information for the memory device is based on memory access from the different sources in the processing system including a central processor and a graphics processor; and wherein the power manager is to load balance among the different sources, including the central processor and the graphics processor.

15. An electronic device comprising:
a memory device to store data; a host hardware platform including a processor device coupled to control a power management system and execute a power manager, and a memory controller device coupled to provide a memory access interface to the memory device, wherein the power management system includes a current sensor to generate current usage information for a memory device based on a measurement of current for the memory device in active operation and performing monitoring of power usage pattern of known traffic;
wherein monitoring comprises receiving sensor input from current sensors in a voltage regulator that provides power to the memory device; and
a power manager to receive the current usage information from the current sensor, determine to load balance among different sources of memory access base

Assignees

• Intel Corp

Inventors

• Cooper Lawrence A
• Song Justin J
• Man Xiuting C
• Aboulenein Nagi
• Cox Christopher E
• Loop Rebecca Z

Classifications

• G06F1/3225

  of memory devices · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic