Voltage regulator control system

Patent metadata

Field	Value
Publication number	US-9851768-B2
Application number	US-201214376136-A
Country	US
Kind code	B2
Filing date	Apr 20, 2012
Priority date	Apr 20, 2012
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A processor power management system and method are disclosed. The system includes a voltage regulator control system that is communicatively coupled to each of a plurality of processors. The voltage regulator control system is to generate a processor voltage that is provided to each of the plurality of processors and to control a magnitude of the processor voltage based on receiving power management request signal s that are provided from each of the plurality of processors.

First claim

What is claimed is:

1. A voltage regulator control system comprising a single voltage regulator, the single voltage regulator communicatively coupled directly to each of a plurality of processors, the single voltage regulator to:
control a magnitude of a processor voltage based on receiving at least one power management request signal from each of the plurality of processors;
generate a processor voltage that is provided to each of the plurality of processors; and
in response to a voltage change request issued by one of the plurality of processors to the single voltage regulator to increase or decrease the processor voltage, transmit an alert signal to each of the remaining plurality of processors.

2. The system of claim 1 , wherein the voltage regulator control system comprises a voltage regulator memory, wherein the voltage regulator control system is to designate respective registers of the voltage regulator memory that are each individually dedicated to each of the respective plurality of processors.

3. The system of claim 1 , wherein the voltage regulator control system is to reduce the processor voltage in response to a power management request signal from one of the plurality of processors in response to each of a remaining plurality of processors operating in a low power mode, such that the processor voltage provides sufficient power to the remaining plurality of processors upon being reduced.

4. The system of claim 1 , wherein each of the plurality of processors is to generate a request to the voltage regulator control system to decrease the processor voltage in response to switching from an active mode to a low voltage mode, and wherein the voltage regulator control system is to provide an alert signal to a respective one of the plurality of processors in response to receiving the request and being unable to reduce the processor voltage based on power required by another one of the plurality of processors.

5. The system of claim 1 , wherein the voltage regulator control system comprises:
a multi-host voltage regulator control system that is communicatively coupled to each of the plurality of processors to transmit and receive power management commands to and from the plurality of processors;
a voltage regulator system communicatively coupled to the multi-host voltage regulator control system to generate and control the magnitude of the processor voltage based on receiving commands that are provided from the multi-host voltage control regulator system.

6. The system of claim 1 , wherein the voltage regulator control system and the plurality of processors are to communicate via a Serial Voltage IDentification (SVID) bus.

7. A method for controlling a processor voltage that is provided to each of a plurality of processors by a single voltage regulator, the method comprising:
receiving, at the single voltage regulator, a voltage increase request signal from a given one of the plurality of processors to increase the processor voltage in response to the given one of the plurality of processors switching from a low power mode to an active mode, and in response, transmit a first alert signal to each of the remaining plurality of processors;
increasing the processor voltage via the single voltage regulator in response to the voltage increase request signal;
receiving, at the single voltage regulator, a voltage decrease request signal from the given one of the plurality of processors to decrease the processor voltage in response to the given one of the plurality of processors switching from the active mode to the low power mode; and
decreasing the processor voltage via the single voltage regulator in response to the voltage decrease request signal and in response to determining that a remaining plurality of processors are operating in the low power mode, and in response, transmit a second alert signal to each of the remaining plurality of processors.

8. The method of claim 7 , further comprising providing a third alert signal to the remaining plurality of processors in response to receiving each of the voltage increase request signal and the voltage decrease request signal.

9. The method of claim 7 , further comprising maintaining a magnitude of the processor voltage in response to the voltage decrease request signal and in response to determining that at least one of the remaining plurality of processors is operating in the active mode.

10. A power management system comprising:
a plurality of processors, each of the plurality of processors switchable between operation in an active mode and a low power mode;
a voltage regulator control system comprising a single voltage regulator, the single voltage regulator communicatively coupled to each of a plurality of processors, the single voltage regulator to:
generate a processor voltage that is provided to each of the plurality of processors;
receive a voltage increase request signal from a first one of the plurality of processors to increase the processor voltage in response to the given one of the plurality of processors switching from a low power mode to an active mode
in response to the first one of the plurality of processors switching to the active mode, increase a magnitude of the processor voltage and transmit a first alert signal to each of the remaining plurality of processors;
receive a voltage decrease request signal from a second one of the plurality of processors to decrease the processor voltage in response to the second one of the plurality of processors switching from the active mode to the low power mode; and
in response to the second one of the plurality of processors switching to the low power mode and a determination that a remaining plurality of processors operates in the low power mode, decrease the magnitude of the processor voltage and transmit a second alert signal to each of the remaining plurality of processors.

11. The system of claim 10 , wherein the voltage regulator control system comprises a voltage regulator memory, wherein the voltage regulator control system is to designate respective registers of the voltage regulator memory that are each individually dedicated to each of the respective plurality of processors.

Assignees

• Hua Chanh V
• Hewlett Packard Entpr Dev Lp

Inventors

• Hua Chanh V

Classifications

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/3237

  by disabling clock generation or distribution · CPC title

• Y02B60/1285

  Cross-Sectional Technologies · mapped topic

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• Y02B60/1221

  Cross-Sectional Technologies · mapped topic