Display device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9851595-B2
Application number	US-201615204913-A
Country	US
Kind code	B2
Filing date	Jul 7, 2016
Priority date	Jan 7, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A display device according to an exemplary embodiment includes: a substrate including a display area and a peripheral area; a thin film transistor positioned in the display area of the substrate; a first electrode connected to the thin film transistor; a roof layer positioned on the first electrode and spaced apart from the first electrode by a microcavity that is interposed between the roof layer and the first electrode; a liquid crystal layer positioned inside the microcavity; an encapsulation layer positioned on the roof layer; a pad portion positioned in the peripheral area of the substrate; and a pillar positioned in the peripheral area of the substrate.

First claim

What is claimed is:

1. A manufacturing method of a display device comprising:
forming a thin film transistor in a display area of a substrate including a display area, a peripheral area, and an extra area;
forming a first electrode to be connected to the thin film transistor;
forming a sacrificial layer on the first electrode;
forming a roof layer on the sacrificial layer;
forming a microcavity between the first electrode and the roof layer by removing the sacrificial layer;
forming an encapsulation layer on the roof layer;
cutting the encapsulation layer positioned on a boundary between the display area and peripheral area of the substrate;
cutting a boundary between the peripheral area and extra area of the substrate; and
removing the encapsulation layer positioned in the peripheral area and extra area of the substrate, and the extra area of the substrate.

2. The manufacturing method of claim 1 , further comprising:
forming a gate line on the substrate; and
forming a data line on the substrate,
wherein the gate line and the data line are connected to the thin film transistor.

3. The manufacturing method of claim 2 , further comprising:
forming, in the peripheral area of the substrate, a gate pad portion connected to the gate line; and
forming, in the peripheral area of the substrate, a data pad portion connected to the data line.

4. The manufacturing method of claim 3 , further comprising:
forming the sacrificial layer on the gate pad portion and the data pad portion; and
forming a dummy microcavity.

5. The manufacturing method of claim 4 , further comprising:
removing the dummy microcavity; and
forming a pillar in the peripheral area of the substrate.

6. The manufacturing method of claim 5 , wherein the pillar includes a first layer that is made of the same material as the roof layer.

7. The manufacturing method of claim 6 , further comprising:
forming a second electrode on the sacrificial layer; and
forming an insulating layer on the second electrode, wherein the pillar further includes:
a second layer that is positioned under the first layer and is made of the same material as the insulating layer, and
a third layer that is positioned under the second layer and is made of the same material as the second electrode.

8. The manufacturing method of claim 6 , further comprising:
forming a second electrode;
forming an interlayer insulating layer interposed between the first electrode and the second electrode; and
forming an insulating layer on the sacrificial layer,
wherein the pillar further includes:
a second layer that is positioned under the first layer and is made of the same material as the insulating layer.

9. The manufacturing method of claim 3 , wherein
the forming of the gate pad portion includes:
forming a gate pad extended from an end portion of the gate line; and
forming a gate contact assistant on the gate pad.

10. The manufacturing method of claim 9 , wherein
the gate pad is made of the same material as the gate line, and
the gate contact assistant is made of the same material as the first electrode.

11. The manufacturing method of claim 3 , wherein
the forming of the data pad portion includes:
forming a data pad extended from an end portion of the data line, and
forming a data contact assistant on the data pad.

12. The manufacturing method of claim 11 , wherein
the data pad is made of the same material as the data line, and
the data contact assistant is made of the same material as the first electrode.

13. The manufacturing method of claim 1 , further comprising:
irradiating a laser to the encapsulation layer positioned on a boundary between the display area and peripheral area of the substrate to cut the encapsulation layer.

14. The manufacturing method of claim 13 , wherein
a region to which a laser is irradiated does not overlap the gate pad portion or the data pad portion.

15. The manufacturing method of claim 13 , wherein
a side surface of the encapsulation layer includes a heat-deformable portion.

Assignees

• Samsung Display Co Ltd

Inventors

• Park Choi Sang
• Kwon Seong Gyu
• Lim Tae Woo

Classifications

• G02F1/133377 Primary

  Cells with plural compartments or having plurality of liquid crystal microcells partitioned by walls, e.g. one microcell per pixel · CPC title

• G02F1/133707

  Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title

• G02F1/133512

  Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title

• G02F1/133514

  Colour filters · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title