Compact and low loss Y-junction for submicron silicon waveguide

Patent metadata

Field	Value
Publication number	US-9851503-B2
Application number	US-201715446375-A
Country	US
Kind code	B2
Filing date	Mar 1, 2017
Priority date	Nov 30, 2012
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.

First claim

What is claimed is:

1. A submicron optical splitter device comprising:
an input port for inputting a beam of light in a propagation direction;
first and second output ports for outputting first and second portions of the beam of light;
a tapered section divided into a plurality of segments between the input port and the output port;
wherein the segments increase in width from the input port to a maximum width proximate a half-way point of the tapered section;
wherein the segments decrease in width towards the first and second output ports, whereby the maximum width is greater than the width of the segment proximate the two output ports.

2. The device according to claim 1 , wherein a plurality of adjacent segments proximate the half way point comprise the same maximum width.

3. The device according to claim 2 , wherein the plurality of adjacent segments comprises four segments.

4. The device according to claim 2 , wherein the input port and the first and second output ports each has a width of 0.5 um.

5. The device according to claim 4 , further comprising a gap between the first and second output ports; wherein the gap has a width of 0.2 um.

6. The device according to claim 5 , wherein the maximum width is 1.4 um.

7. The device according to claim 3 , wherein a total length of the plurality of segments is 2 um.

8. The device according to claim 1 , wherein the tapered section is symmetrical about the propagation direction to ensure balanced output at the first and second output ports.

9. The device according to claim 1 , wherein the plurality of segments comprises at least 13 segments.

10. The device according to claim 1 , wherein the plurality of segments comprises segments of equal length.

11. The device according to claim 1 , wherein the tapered section comprises silicon with a silicon oxide cladding.

Assignees

• Elenion Tech Llc

Inventors

• Liu Yang
• Ma Yangjin
• Shi Ruizhi
• Hochberg Michael J
• Zhang Yi
• Yang Shuyu
• Baehr-Jones Thomas Wetteland

Classifications

• G02B2006/1215

  Splitter · CPC title

• G02B6/125 Primary

  Bends, branchings or intersections · CPC title

• G02B6/107

  Subwavelength-diameter waveguides, e.g. nanowires · CPC title

• G02B6/2808

  using a mixing element which evenly distributes an input signal over a number of outputs · CPC title

• G06N3/126

  Evolutionary algorithms, e.g. genetic algorithms or genetic programming · CPC title