Image pixels having processed signal storage capabilities

Patent metadata

Field	Value
Publication number	US-9848141-B2
Application number	US-201615151078-A
Country	US
Kind code	B2
Filing date	May 10, 2016
Priority date	May 10, 2016
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

An image sensor may include an array of image sensor pixels. Each image sensor pixel may have signal storage capabilities implemented through a write-back supply line and a control transistor for the supply line. Each image sensor pixel may output pixel values over column lines to switching circuitry. The switching circuitry may route the pixel values to signal processing circuitry. The signal processing circuitry may perform analog and/or digital processing operations utilizing analog circuits or pinned diode devices for image signal processing on the pixel values to output processed pixel values. The processing circuitry may send the processed pixel values back to the array. This allows the array to act as memory circuitry to support processing operations on processing circuitry in close proximity to the array. Configured this way, signal processing can be performed in close proximity to the array without having to move pixel signals to peripheral processing circuitry.

First claim

What is claimed is:

1. An image sensor, comprising:
a plurality of image sensor pixels that generates a pixel value, wherein a given one of the image sensor pixels comprises a charge storage region; and
processing circuitry that generates a processed pixel value based on the generated pixel value, wherein the given image sensor pixel is configured to store the processed pixel value on the charge storage region, wherein the processing circuitry comprises an accumulator, wherein the accumulator comprises a pinned charge storage element, and wherein the accumulator stores the pixel value and generates an accumulated pixel value based on the stored pixel value.

2. The image sensor defined in claim 1 , wherein the charge storage region comprises a photodiode.

3. The image sensor defined in claim 2 further comprising:
a write-back input line; and
a control gate, wherein the write-back input line is coupled to a first terminal of the control gate and the photodiode is coupled to a second terminal of the control gate.

4. The image sensor defined in claim 3 , wherein the control gate comprises an anti-blooming transistor.

5. The image sensor defined in claim 1 , wherein the charge storage region comprises a floating diffusion node.

6. The image sensor defined in claim 5 further comprising:
a write-back input line; and
a control gate, wherein the write-back input line is coupled to a first terminal of the control gate and the floating diffusion node is coupled to a second terminal of the control gate.

7. The image sensor defined in claim 1 , wherein the pixel value is generated in response to light, further comprising:
a light shielding structure that covers the charge storage region.

8. The image sensor defined in claim 1 , wherein the plurality of image sensor pixels and the processing circuitry are both formed on a shared integrated circuit substrate.

9. The image sensor defined in claim 1 , wherein the processing circuitry further comprises compensation circuitry that is configured to compensate for a non-linear relationship between voltage and capacitance in a charge storage well on the accumulator.

10. The image sensor defined in claim 9 , wherein the processing circuitry further comprises:
analog-to-digital conversion circuitry, wherein the analog-to-digital conversion circuitry receives the accumulated pixel value and generates a corresponding processed digital signal; and
digital-to-analog conversion circuitry, wherein the digital-to-analog conversion circuitry receives the processed digital signal and generates the processed pixel value based on the processed digital signal.

11. A method of operating an image sensor that includes an array of image sensor pixels, switching circuitry, and processing circuitry, the method comprising:
with the array of image sensor pixels, generating pixel values;
with the switching circuitry, routing the generated pixel values from the array of image sensor pixels to accumulator circuitry in the processing circuitry;
with the accumulator circuitry in the processing circuitry, generating processed pixel values based on the pixel values generated by the array of image sensor pixels; and
at the array of image sensor pixels, storing the processed pixel values.

12. The method defined in claim 11 , wherein the processing circuitry comprises a pinned photodiode and wherein the pixel values comprise first and second sets of pixel values, the method further comprising:
with the processing circuitry and the pinned photodiode, performing a weighted addition operation on the first set of pixel values; and
with the processing circuitry and the pinned photodiode, performing a weighted subtraction operation on the second set of pixel values.

13. The method defined in claim 11 further comprising:
with the processing circuitry, generating metadata that identifies interest points in an imaged scene from the generated pixel values; and
with the processing circuitry, performing object recognition operations using the generated metadata.

14. The method defined in claim 11 , further comprising:
with the processing circuitry, reading out a plurality of pixel values from a plurality of image sensor pixels within the array of image sensor pixels, wherein the plurality of image sensor pixels forms a subarray within the array of image sensor pixels.

15. The method defined in claim 11 further comprising:
with the processing circuitry, comparing a first plurality of pixel values from a first plurality of image sensor pixels within the array of image sensor pixels with a second plurality of pixel values from a second plurality of image sensor pixels within the array of image sensor pixels, wherein the second plurality of pixel values are previously processed pixel values stored at the array of image sensor pixels.

16. The method defined in claim 11 further comprising:
refreshing the processed pixel values stored at the array of image sensor pixels.

17. A system, comprising:
a central processing unit;
memory;
a lens;
input-output circuitry; and
an imaging device, wherein the imaging device comprises:
an array of image sensor pixels that generates pixel signals;
accumulator circuitry that receives the pixel signals and that performs processing operations on the pixel signals to generate processed pixel signals;
a communications path, wherein the accumulator circuitry conveys the processed pixel signals to the array of image sensor pixels for storage on at least one image sensor pixel in the array over the communications path;
readout circuitry that is separated from the accumulator circuitry, wherein the readout circuitry is configured to receive the generated pixel signals; and
switching circuitry configured to selectively route the generated pixel signals to the accumulator circuitry.

18. The system defined in claim 17 , wherein the switching circuitry is coupled to the communications path, the readout circuitry, and the array and wherein the imaging device further comprises:
shift register circuitry, wherein the shift register circuitry is configured to control the switching circuitry to route the generated pixel signals to one or both of the circuitry and the readout circuitry.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Panicacci Roger
• Mlinar Marko

Classifications

• H04N25/622 Primary

  by controlling anti-blooming drains · CPC title

• H04N23/10

  for generating image signals from different wavelengths · CPC title

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N2209/045

  using mosaic colour filter · CPC title

• H04N5/378

  Electricity · mapped topic