Frequency synthesizer with microcode control

Patent metadata

Field	Value
Publication number	US-9847869-B1
Application number	US-201615210204-A
Country	US
Kind code	B1
Filing date	Jul 14, 2016
Priority date	Oct 23, 2015
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A frequency synthesizer with microcode control that allows one or more programmable circuits of a frequency synthesizer system to be programmed using a plurality of microcode instructions. A method includes, setting a frequency synthesizer system to operate in a microcode mode, programming the frequency synthesizer system for microcode execution of a plurality of microcode instructions and executing the plurality of microcode instructions at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system.

First claim

We claim:

1. A method for controlling a frequency synthesizer system, the method comprising:
setting the frequency synthesizer system to operate in a microcode mode, the frequency synthesizer system including a data memory circuit having a master stage, a slave stage and a switch that extends between the master stage and the slave stage;
programming the frequency synthesizer system for microcode execution of a plurality of microcode instructions by disabling the switch, loading a plurality of microcode instructions into the master stage of the data memory circuit and storing a sequence of addresses for the plurality of microcode instructions in a memory of the frequency synthesizer system; and
executing the plurality of microcode instructions at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system.

2. The method of claim 1 , wherein the one or more programmable circuits comprises a phase locked loop (PLL) circuit and wherein executing the microcode instructions at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system further comprises executing microcode at the frequency synthesizer system to control one or more behaviors of the PLL circuit.

3. The method of claim 1 , wherein the one or more programmable circuits comprises an output buffer circuit and wherein executing microcode at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system further comprises executing microcode at the frequency synthesizer system to control one or more behaviors of the output buffer circuit.

4. The method of claim 1 , wherein setting the frequency synthesizer system to operate in microcode mode further comprises, providing a microcode control signal through a logical interface of the frequency synthesizer system.

5. The method of claim 1 , wherein executing the microcode at the frequency synthesizer system to control one or more behaviors of one or more programmable circuits of the frequency synthesizer system further comprises:
enabling a program counter for the sequence of addresses stored in the memory;
executing each of the plurality of microcode instructions stored in the master stage of the data memory circuit, using the program counter to step through the sequence of addresses stored in the memory, to generate one or more programmed control values;
closing the switch to store the one or more programmed control values in the slave stage of the data memory circuit; and
controlling one or more behaviors of one or more programmable circuits of the frequency synthesizer system using the one or more programmed control values in the slave stage of the data memory circuit.

6. The method of claim 1 , wherein the one or more programmable circuits of the frequency synthesizer system are selected from a phase locked loop (PLL) circuit and an output buffer circuit.

7. The method of claim 1 , wherein the microcode instructions are processor overclocking microcode instructions.

8. The method of claim 1 , wherein loading a plurality of microcode instructions into the master stage of the data memory circuit further comprises, writing the plurality of microcode instructions into the master stage of the data memory circuit through a logical interface of the frequency synthesizer system.

9. A method for controlling a frequency synthesizer system, the method comprising:
initiating a power-up sequence for a processor board comprising the frequency synthesizer system, the frequency synthesizer system including a data memory circuit having a master stage, a slave stage and a switch that extends between the master stage and the slave stage;
initializing the frequency synthesizer system in a default mode after the initiating a power-up sequence for the processor board by loading one or more default control values into the master stage of the data memory circuit, loading the one or more default control values from the master stage to the slave stage of the data memory circuit through the switch, and controlling one or more behaviors of one or more programmable circuits of the frequency synthesizer system using the one or more default control values in the slave stage of the data memory circuit;
setting the frequency synthesizer system to operate in a microcode mode after the initiating a power-up sequence;
programming the frequency synthesizer system for microcode execution of a plurality of microcode instructions; and executing the plurality of microcode instructions at the frequency synthesizer system to control the one or more behaviors of the one or more programmable circuits of the frequency synthesizer system.

10. The method of claim 9 , wherein loading one or more default control values into the master stage of the data memory circuit of the frequency synthesizer system further comprises, loading one or more default control values from a Read Only Memory (ROM) circuit into the master stage of the data memory circuit of the frequency synthesizer system.

11. A frequency synthesizer system comprising:
a phase locked loop (PLL) circuit including a reference counter circuit, a charge pump circuit, a loop filter circuit, a feedback counter circuit and an output divider circuit;
a logical interface;
a data memory circuit having a master stage, a slave stage and a switch that extends between the master stage and the slave stage, the data memory circuit coupled to the logical interface and coupled to one or more of the reference counter circuit, the loop filter circuit, the feedback counter circuit and the output divider circuit, the data memory circuit for storing a plurality of microcode instructions to control one or more behaviors of the PLL circuit;
a control memory circuit coupled to the logical interface and the data memory circuit, the control memory circuit storing a sequence of addresses for the plurality of microcode instructions stored in the data memory circuit; and
a program counter coupled to the control memory circuit and the logical interface, the program counter for stepping through the sequence of addresses stored in the control memory circuit to execute the plurality of microcode instructions stored in the data memory circuit for controlling the one or more behaviors of the PLL circuit.

12. A frequency synthesizer system comprising:
one or more programmable circuits;
a logical interface;
a data memory circuit coupled to the logical interface and to the one or more programmable circuits, the data memory circuit including a master stage for storing a plurality of microcode instructions to control one or more behaviors of the one or more programmable circuits, a slave stage for storing one or more programmed control values resulting from the execution of the microcode instructions stored in the master stage, the programmed control values to control the one or more behaviors of the one or more programmable circuits, and a switch coupled between the master stage and the slave stage;
a control memory circuit coupled to the logical interface and the data memory circuit, the control memory circuit storing a sequence of addresses for the plurality of microcode instructions; and

a program counter coupled to the control memory circuit and the logical interface, the program counter for stepping through the sequence of addresses to execute the plurality of microcode instructions.

13. The frequency synthesizer system of claim 12 , wherein the microcode instructions are processor overclocking microcode instructions.

Assignees

• Integrated Device Tech

Inventors

• Wu Chung-Yu
• Chan Wei-Ching
• Hsu John
• Hsiao Cheng Wen

Classifications

• H04L2012/5681

  Buffer or queue management · CPC title

• H04L7/033 Primary

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/104 Primary

  using an additional signal from outside the loop for setting or controlling a parameter in the loop (H03L7/107, H03L7/12 take precedence) · CPC title

• H03L7/183

  a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number {(H03L7/1806 takes precedence)} · CPC title