Method and apparatus for reduced HARQ buffer storage

Patent metadata

Field	Value
Publication number	US-9847853-B1
Application number	US-201615008779-A
Country	US
Kind code	B1
Filing date	Jan 28, 2016
Priority date	Jan 28, 2016
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Automatic Repeat Request (ARQ) protocol is used in many modern telecommunication systems for improved link level reliability. Hybrid ARQ (HARQ) protocol takes advantage of the retransmissions in ARQ to enable the receiver to decode the currently received data by combining it with all the previously received transmissions that were not successfully decoded. Each successive retransmission improves the probability of correctly decoding the data. To support HARQ, the receiver is required to store the previously received unsuccessful transmissions for combining with future retransmissions. The storage of the previously received unsuccessful transmissions can be very large depending on type of the HARQ protocol used. A method and apparatus are disclosed that enable reduced memory storage requirements while maintaining the HARQ performance requirements. The reduced memory requirements result in reduced cost, reduced power consumption and lowered cost.

First claim

The invention claimed is:

1. A method for storing, in a memory, Log Likelihood Ratios (LLR) for a Hybrid Automatic Repeat Request (HARQ) protocol in a communication system,
wherein the memory has a size (i) less than a maximum size required by the HARQ protocol for a worst case Transport Block decoding condition at a communication device of the communication system, (ii) satisfying Transport Block Error (BLER) rate and throughput performance of the HARQ protocol, and (iii) to store all transmissions of initial Redundancy Versions (RV0) respectively for a predetermined number of Transport Blocks, and
in which the RV0 transmissions respectively for the predetermined number of Transport Blocks include less than all systematic bits of the predetermined number of Transport Blocks,
the method comprising:
controlling, by a processing device,
decoding of a first Code Block of a first Transport Block of the Transport Blocks by combining an LLR of a RV0 of the first Code Block of the first Transport Block for which decoding was unsuccessful with an LLR of a currently retransmitted Redundancy Version (RVI) of the first Code Block of the first Transport Block, in which the LLR of the RV0 of the first Code Block of the first Transport Block is stored in a first position of the memory corresponding to the first Transport Block,
when the decoding of the first Code Block of the first Transport Block by the combining is unsuccessful, generating a redundancy check failure indication and transmitting a negative acknowledgement (NACK) to a base station of the system from which Redundancy Versions of the Code Blocks respectively of the Transport Blocks are transmitted,
when space in the memory for storing the LLR of the RVI of the first Code Block of the first Transport Block is not available and a newly received LLR of the first Transport Block is from a Redundancy Version (RV) different from an RV for the first Transport Block stored in the memory, the newly received LLR of the first Transport Block not to be stored in the memory,
when the newly received LLR of the first Transport Block is from a same RV as a given RV for the first Transport Block having a given LLR thereof stored in the memory, storing a result of combining the newly received LLR for the first Transport Block with the given LLR for the first Transport Block stored in the memory, at a position in the memory at which the given LLR corresponding to the first Transport Block is stored, and
when decoding for the first Transport Block is successful, releasing the first position in the memory corresponding to the first Transport Block.

2. The method of claim 1 ,
wherein the decoding of the Code Blocks respectively of the Transport Blocks includes a cyclic redundancy check (CRC).

3. The method of claim 1 ,
controlling, by the processing device, when the first position in the memory corresponding to the first Transport Block has been released and a second position in the memory corresponding to a second Transport Block of the Transport Blocks is full, storing a currently retransmitted RVI for the second Transport Block in the first position in the memory.

4. The method of claim 1 ,
controlling, by the processing device, the decoding of the first Code Block of the first Transport Block by combining the LLR of the RV0 of the first Code Block of the first Transport Block for which decoding was unsuccessful with the LLR of the currently retransmitted (RVI) of the first Code Block of the first Transport Block and an LLR of each previously retransmitted RVI of the first Code Block of the first Transport Block, in which the LLR of each previously retransmitted RVI of the first Code Block of the first Transport Block is stored at a respective position in the memory.

5. The method of claim 1 ,
controlling, by the processing device, when a given position in the memory corresponding to a given Transport Block of the Transport Blocks has a size configured to store initial offset Systematic bits external to an RV0 for the given Transport Block and a retransmission RVI for the given Transport Block including the initial offset Systematic bits is received, storing an LLR for the initial offset Systematic bits in the given position in the memory corresponding to the given Transport Block which is storing an LLR for the RV0 of the given Transport Block.

6. The method of claim 1 ,
wherein the size of the memory is determined according to a highest code rate for the communication system, and
wherein the communication system is a 3 rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) wireless communication system.

7. An apparatus for storing, in a memory, Log Likelihood Ratios (LLR) for a Hybrid Automatic Repeat Request (HARQ) protocol in a communication system,
wherein the memory has a size (i) less than a maximum size required by the HARQ protocol for a worst case Transport Block decoding condition at a communication device of the communication system, (ii) satisfying Transport Block Error (BLER) rate and throughput performance of the HARQ protocol, and (iii) to store all transmissions of initial Redundancy Versions (RV0) respectively for a predetermined number of Transport Blocks, and
in which the RV0 transmissions respectively for the predetermined number of Transport Blocks include less than all systematic bits of the predetermined number of Transport Blocks,
the apparatus comprising:
circuitry configured to control:
decoding of a first Code Block of a first Transport Block of the Transport Blocks by combining an LLR of a RV0 of the first Code Block of the first Transport Block for which decoding was unsuccessful with an LLR of a currently retransmitted Redundancy Version (RVI) of the first Code Block of the first Transport Block, in which the LLR of the RV0 of the first Code Block of the first Transport Block is stored in a first position of the memory corresponding to the first Transport Block,
when the decoding of the first Code Block of the first Transport Block by the combining is unsuccessful, generating a redundancy check failure indication and transmitting a negative acknowledgement (NACK) to a base station of the system from which Redundancy Versions of the Code Blocks respectively of the Transport Blocks are transmitted,
when space in the memory for storing the LLR of the RVI of the first Code Block of the first Transport Block is not available and a newly received LLR of the first Transport Block is from a Redundancy Version (RV) different from an RV for the first Transport Block stored in the memory, the newly received LLR of the first Transport Block not to be stored in the memory,
when the newly received LLR of the first Transport Block is from a same RV as a given RV for the first Transport Block having a given LLR thereof stored in the memory, storing a result of combining the newly received LLR for the first Transport Block with the given LLR for the first Transport Block stored in the memory, at a position in the memory at which the given LLR corresponding to the first Transport Block is stored, and
when decoding for the first Transport Block is successful, releasing the first position in the memory corresponding to the first Transport Block.

8. The apparatus of claim 7 ,
wherein the decoding of the Code Blocks respectively of the Transport Blocks includes a cyclic redundancy check (CRC).

9. The apparatus of claim 7 ,
wherein the circuitry is configured to control, when the first position in the memory corresponding to the first Transport Block has been released and a second position in the memory corresponding to a second Transport Block of the Transport Blocks is full, storing a currently retransmitted RVI for the second Transport Block in the first p

Assignees

• Mbit Wireless Inc

Inventors

• Patel Bhaskar

Classifications

• H03M13/095

  Error detection codes other than CRC and single parity bit codes · CPC title

• H04L1/1835

  Buffer management · CPC title

• H04L1/1819 Primary

  with retransmission of additional or different redundancy · CPC title

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• H04L1/1812 Primary

  Hybrid protocols; Hybrid automatic repeat request [HARQ] · CPC title