PAM4 transceivers for high-speed communication

Patent metadata

Field	Value
Publication number	US-9847839-B2
Application number	US-201615061923-A
Country	US
Kind code	B2
Filing date	Mar 4, 2016
Priority date	Mar 4, 2016
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

First claim

What is claimed is:

1. A transceiver system comprising:
an input terminal for receiving input data stream, the first data stream being characterized by a first frequency;
a clock generation module being configured to generate a clock signal based at least on the data stream;
a regulator coupled to a power source, the regulator being configured to attenuate noises associated with the power source;
a first voltage gain amplifier being configured to generate a first driving signal, the first voltage gain amplifier comprising an integrated equalizer, the first voltage gain amplifier being characterized by a bandwidth of at least 13 GHz;
a track and hold (T/H) module comprising a first plurality of T/H circuits, the first plurality of T/H circuits being controlled by the first driving signal for holding the input data stream at a second frequency;
a shift and hold (SH) buffer comprising a first plurality of buffer units corresponding to the first plurality of T/H circuits, the first plurality of buffer units being configured to store a first plurality of samples based on the input data stream;
an analog-to-digital converter (ADC) module comprising a first plurality of ADC circuits being configured to convert the first plurality of samples;
a digital signal processor (DSP) being configured to generate output data stream based at least one the first plurality of samples; and
an output terminal for transmitting the output data stream.

2. The system of claim 1 further comprising a delay-lock loop (DLL) coupled to the ADC module for generating timing phases.

3. The system of claim 1 wherein the second frequency is at about half of the first frequency.

4. The system of claim 1 further comprising a second voltage gain amplifier being configured to generate a second drive signal for a second plurality of T/H circuits.

5. The system of claim 1 wherein the DSP comprises a skew control module for aligning the first plurality of samples.

6. The system of claim 1 wherein multiple ADC circuits correspond to a single SH buffer unit.

7. The system of claim 1 wherein the DSP comprises a set of parallel feed forward equalizer for performing channel equalization.

8. The system of claim 1 further comprising a modulator for modulating the first output data stream for transmission over an optical communication link.

9. The system of claim 1 wherein the output data stream is modulated in a pulse-amplitude modulation 4 (PAM4) format.

10. The system of claim 1 wherein the regulator performs feed-forward injection for attenuating the noises.

11. The system of claim 1 wherein the first integrated voltage gain amplifier is characterized by a gain range of at least 12 dB.

12. The system of claim 1 wherein the clock generation module comprising a phase-lock loop (PLL) circuit for performing clock recovery using the input data stream.

13. The device of claim 1 wherein each of the ADC circuits comprises a successive approximation register.

14. A transceiver system comprising:
an input terminal for receiving input data stream, the first data stream being characterized by a first frequency;
a clock generation module being configured to generate a clock signal based at least one the data stream;
a first voltage gain amplifier being configured to generate a first driving signal, the first voltage gain amplifier comprising an integrated equalizer, the first voltage gain amplifier being characterized by a gain range of at least 12 dB in 0.1 dB steps;
a track and hold (T/H) module comprising a first plurality of T/H circuits, the first plurality of T/H circuits being controlled by the first driving signal for holding the input data stream at a second frequency;
a shift and hold (SH) buffer comprising a first plurality of buffer units corresponding to the first plurality of T/H circuits, the first plurality of buffer units being configured to store a first plurality of samples based on the input data stream;
an analog-to-digital converter (ADC) module comprising a first plurality of ADC circuits being configured to convert the first plurality of samples;
a digital signal processor (DSP) being configured to generate output data stream based at least one the first plurality of samples, the DSP comprising a decision feedback equalizer for reducing errors; and
an output terminal for transmitting the output data stream.

15. The apparatus of claim 14 wherein the DSP comprises a forward-error correction (FEC) encoder.

16. The apparatus of claim 14 further comprising a Mach-Zehnder modulator (MZM) for modulating the output data stream.

17. The apparatus of claim 14 wherein the DSP is configured to provide eye modulation.

18. A transceiver system comprising:
an input terminal for receiving input data stream, the first data stream being characterized by a first frequency;
a clock generation module being configured to generate a clock signal based at least one the data stream;
a first voltage gain amplifier being configured to generate a first driving signal, the first voltage gain amplifier comprising an integrated equalizer and a transconductance boosted source degeneration;
a second voltage gain amplifier being configured generate a second driving signal;
a track and hold (T/H) module comprising a first plurality of T/H circuits and a second plurality of T/H circuits, the first plurality of T/H circuits being controlled by the first driving signal for holding the input data stream at a second frequency, the second T/H circuit being controlled by the second driving signal for holding the input data stream at the second frequency;
a shift and hold (SH) buffer comprising a first plurality of buffer units corresponding to the first plurality of T/H circuits and a second plurality of buffer units corresponding to the second plurality of T/H circuits, the first plurality of buffer units being configured to store a first plurality of samples based on the input data stream;
an analog-to-digital converter (ADC) module comprising a first plurality of ADC circuits being configured to convert the first plurality of samples;
a digital signal processor (DSP) being configured to generate output data stream based at least one the first plurality of samples; and
an output terminal for transmitting the output data stream.

19. The device of claim 18 wherein the input terminal comprises a continuous-time linear equalizer (CTLE) for processing the input data stream.

Assignees

• Inphi Corp

Inventors

• Gopalakrishnan Karthik
• Riani Jamal
• Tiruvur Arun

Classifications

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/23

  with pulse counters or frequency dividers · CPC title

• H04L7/0331

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title