Facilitation of increased locking range transistors

Patent metadata

Field	Value
Publication number	US-9847784-B2
Application number	US-201715425597-A
Country	US
Kind code	B2
Filing date	Feb 6, 2017
Priority date	Jul 27, 2015
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Transistors can be used for a variety of electronic-based applications. Therefore, transistor efficiency and performance is of importance. An apparatus is presented herein to increase the locking range of transistors by leveraging cross-coupled injection transistors in conjunction with symmetry injection transistors. The transistor efficiency can also be increase by reducing a parasitic capacitance associated with the components of the transistor.

First claim

What is claimed is:

1. A method, comprising:
forming a four-terminal transistor comprising a first injection transistor and a second injection transistor and a first cross-coupled transistor and a second cross-coupled transistor on a single transistor cell, wherein the first cross-coupled transistor, and the second cross-coupled transistor are n-type metal-oxide-semiconductor field-effect transistors;
connecting a first gate of the second cross-coupled transistor, a second drain of the first injection transistor and of the first cross-coupled transistor to a first terminal;
connecting a first drain of the second cross-coupled transistor and of the second injection transistor, and a fourth gate of the first cross coupled transistor to a second terminal;
connecting a second gate of the second injection transistor, and a third gate of the first injection transistor to a third terminal;
connecting a first source of the second cross-coupled transistor, a second source of the first injection transistor and the second injection transistor, and a third source of the first cross-coupled transistor to a fourth terminal;
cross-connecting the first gate of the second cross-coupled transistor with the second drain of the first cross-coupled transistor; and
cross-connecting the first drain of the second cross-coupled transistor with the fourth gate of the first cross-coupled transistor.

2. The method of claim 1 , further comprising:
connecting the second source of the first injection transistor and the second injection transistor to a ground.

3. The method of claim 2 , wherein the ground is a first ground, further comprising:
connecting the first source of the second cross-coupled transistor and the third source of the first cross-coupled transistor to a second ground.

4. The method of claim 1 , further comprising:
connecting the first source of the second cross-coupled transistor and the second source of the first injection transistor and the second injection transistor and the third source of the first cross-coupled transistor to a ground.

5. The method of claim 1 , wherein the forming comprises integrating the first injection transistor, the second injection transistor, the first cross-coupled transistor, and the second cross-coupled transistor into a standard radio frequency transistor cell.

6. The method of claim 1 , further comprising:
connecting the first terminal and the second terminal to an inductor.

7. The method of claim 6 , wherein the inductor comprises an electrical contact at a midpoint of the inductor.

8. A method, comprising:
forming a first injection transistor comprising a second source, a third gate and a second drain on a single transistor cell;
forming a second injection transistor comprising the second source, a second gate and a first drain on the single transistor cell, wherein the first injection transistor and the second injection transistor share the second source, which is connected to a first ground;
forming a first cross-coupled transistor comprising a third source, a fourth gate and the second drain on the single transistor cell, wherein the first cross-coupled transistor and the first injection transistor share the second drain;
forming a second cross-coupled transistor comprising a first source, a first gate and the first drain on the single transistor cell, wherein the second cross-coupled transistor and the second injection transistor share the first drain, wherein the first cross-coupled transistor and the second cross-coupled transistor are cross-coupled, and wherein the first cross-coupled transistor, and the second cross-coupled transistor are n-type metal-oxide-semiconductor field-effect transistors;
cross-coupling the first cross-coupled transistor and the second cross-coupled transistor;
connecting the fourth gate of the first cross-coupled transistor to the first drain of the second cross-coupled transistor;
connecting the second drain of the first cross-coupled transistor to the first gate of the second cross-coupled transistor;
connecting the third source of the first cross-coupled transistor and the first source of the second cross-coupled transistor are connected to a second ground
forming a first node comprising:
the first gate of the second cross-coupled transistor; and
the second drain, wherein the first cross-coupled transistor and the first injection transistor share the second drain;

forming a second node comprising:
the fourth gate of the first cross-coupled transistor; and
the first drain, wherein the second cross-coupled transistor and the second injection transistor share the first drain; and

forming a third node comprising:
the second gate of the second injection transistor; and
the third gate of the first injection transistor;

forming a fourth node comprising:
the first source of the second cross-coupled transistor; and
the second source, wherein the first injection transistor and the second injection transistor share the second source; and
the third source of the first cross-coupled transistor.

9. The method of claim 8 , wherein the first ground and the second ground comprises a ground.

10. The method of claim 8 , wherein the first injection transistor and the second injection transistor are n-type metal-oxide-semiconductor field-effect transistors.

11. The method of claim 8 , wherein the first cross-coupled transistor is an n-type metal-oxide-semiconductor field-effect transistor.

12. The method of claim 8 , wherein the second cross-coupled transistor is an n-type metal-oxide-semiconductor field-effect transistor.

13. The method of claim 8 , further comprising:
connecting the first node and the second node to an inductor.

14. The method of claim 13 , wherein the inductor comprises an electrical contact at a midpoint of the inductor.

15. A single cell transistor, comprising:
a first injection transistor, comprising:
a second drain;
a third gate; and
a second source;

a second injection transistor, comprising:
a first drain;
a second gate; and
the second source;

a first cross-coupled transistor, wherein the first cross-coupled transistor is an n-type metal-oxide-semiconductor field-effect transistor, comprising:
the second drain;
a fourth gate; and
a third source;

a second cross-coupled transistor, wherein the second cross-coupled transistor is an n-type metal-oxide-semiconductor field-effect transistor, comprising:
the first drain;
a first gate; and
a first source;

a first terminal, wherein the first gate and the second drain are connected to the first terminal;
a second terminal, wherein the first drain and the fourth gate are connected to the second terminal;
a third terminal, wherein the second gate and the third gate are connected to the third terminal; and
a fourth terminal, wherein the first source, the second source and the third source are connected to the fourth terminal.

16. The transistor of claim 15 , wherein the first gate is cross-connected with the second drain.

17. The transistor of claim 16 , wherein the first drain is cross-connected with the fourth gate.

18. The transistor of claim 15 , wherein the first terminal and the second terminal are connected to an inductor.

19. The transistor of claim 18 , wherein the inductor comprises an electrical contact at a midpoint of the inductor.

20. The transistor of claim 15 , wherein the first injection transistor and the second injection transistor share the second source.

Assignees

• Univ City Hong Kong

Inventors

• Xue Quan
• Zhou Haifeng
• Shum Kam Man

Classifications

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H01L21/76895

  Electricity · mapped topic

• H03B19/14

  by means of a semiconductor device · CPC title

• H01L21/823475

  Electricity · mapped topic