Methods and apparatus for resistive random access memory (RRAM)

Patent metadata

Field	Value
Publication number	US-9847478-B2
Application number	US-201213416183-A
Country	US
Kind code	B2
Filing date	Mar 9, 2012
Priority date	Mar 9, 2012
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Methods and apparatuses for a resistive random access memory (RRAM) device are disclosed. The RRAM device comprises a bottom electrode, a resistive switching layer disposed on the bottom electrode, and a top electrode disposed on the resistive switching layer. The resistive switching layer is made of a composite of a metal, Si, and O. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.

First claim

What is claimed is:

1. A resistive random access memory (RRAM), comprises:
a bottom electrode disposed on a substrate;
a resistive switching layer disposed over the bottom electrode, the resistive switching layer being a composite of a metal, silicon, and oxygen, the resistive switching layer being formed by a process consisting essentially of:
oxidation of a metal silicide of the metal,
co-deposition of the metal and silicon in oxygen ambiance,
co-deposition of a metal oxide of the metal and silicon, or
co-deposition of a metal oxide of the metal and silicon oxide;

a top electrode disposed over the resistive switching layer; and
a continuous tunnel barrier layer disposed under the top electrode and over the bottom electrode, wherein at least one of the bottom electrode and the top electrode comprises a plurality of sub-layers, each sub-layer having a substantially uniform thickness in one dimension in a cross-sectional view, and wherein at least two sub-layers comprise a metal material.

2. The RRAM of claim 1 , wherein the bottom electrode comprises a material, selected from a group consisting essentially of TaN, TiN, TiAlN, TiW, Pt, W, Ru, and combinations thereof.

3. The RRAM of claim 1 , wherein a thickness of the bottom electrode is between a range about 5-500 nm.

4. The RRAM of claim 1 , wherein a thickness of the resistive switching layer is between a range about 1-100 nm.

5. The RRAM of claim 1 , wherein the top electrode comprises a material, selected from a group consisting essentially of TaN, TiN, TiAlN, TiW, Pt, W, Ru, and combinations thereof.

6. The RRAM of claim 1 , wherein a thickness of the top electrode is between a range about 5-500 nm.

7. The RRAM of claim 1 , wherein the substrate comprises a complementary metal oxide semiconductor (CMOS) circuit, an isolation structure, a diode, or a capacitor.

8. The RRAM of claim 1 , wherein the metal of the resistive switching layer comprises a singular or a plural combination of W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, or Cr.

9. The RRAM of claim 1 , further comprising:
a continuous tunnel barrier layer of insulating material disposed in direct contact with the resistive switching layer between the top electrode or the bottom electrode, wherein the insulating material comprises a material selected from a group consisting essentially of Al 2 O 3 , SiO 2 , MgO, TiO 2 , TiAlON, TaO 2 , TaAlON, SiN, SiON, or combinations thereof.

10. The RRAM of claim 1 , wherein the resistive switching layer is formed by co-deposition of metal and silicon in oxygen ambiance.

11. A resistive random access memory (RRAM), comprises:
a bottom electrode disposed on a substrate;
a resistive switching layer disposed on the bottom electrode, the resistive switching layer comprising a composite of tungsten, silicon, and oxygen and formed by a process consisting essentially of:
oxidation of tungsten silicide,
co-deposition of tungsten and silicon in oxygen ambiance,
co-deposition of tungsten oxide and silicon, or
co-deposition of tungsten oxide and silicon oxide;

a top electrode disposed on the resistive switching layer; and
a tunnel barrier layer between the bottom electrode and the top electrode, wherein at least one of the bottom electrode and the top electrode comprises two sub-layers, each sub-layer having a planar top and bottom in a cross-sectional view, and wherein the two sub-layers comprise different metal materials.

12. The RRAM of claim 11 , wherein the metal materials of the two sub-layers are selected from a group consisting essentially of TaN, TiN, TiAlN, TiW, Pt, W, Ru, or combinations thereof.

13. The RRAM of claim 11 , wherein the tunnel barrier layer comprises a material selected from a group consisting essentially of Al 2 O 3 , SiO 2 , MgO, TiO 2 , TiAlON, TaO 2 , TaAlON, SiN, SiON, or combinations thereof.

14. The RRAM of claim 11 , wherein the resistive switching layer is formed by co-deposition of metal oxide and silicon or silicon oxide.

15. A resistive random access memory (RRAM), comprising:
a substrate comprising a complementary metal oxide semiconductor (CMOS) circuit, an isolation structure, a diode, or a capacitor;
a top electrode layer comprising first and second sub-layers of different metal materials, each of the first and second sub-layers respectively having a substantially uniform thickness in a first dimension in cross-sectional view and electrically interfacing to each other in a second dimension perpendicular to the first dimension;
a bottom electrode layer disposed in contact with the substrate in the second dimension and electrically connected to a drain electrode of a transistor, the bottom electrode layer comprising third and fourth sub-layers of different metal materials, each of the third and fourth sub-layers respectively having a substantially uniform thickness in the first dimension and electrically interfacing to each other in the second dimension, the different metal materials of the top and bottom electrode layers selected from a group consisting essentially of TaN, TiN, TiAlN, TiW, Pt, W, Ru, or combinations thereof;
a resistive switching layer disposed between the top electrode layer and bottom electrode layer and electrically connected to the top or bottom electrode layer, material of the resistive switching layer being a metal, silicon, and oxygen as an oxide, wherein the metal of the resistive switching layer comprises a singular or a plural combination of W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, or Cr, wherein the resistive switching layer is formed by a process consisting essentially of:
oxidation of a metal silicide of the metal,
co-deposition of the metal and silicon in oxygen ambiance,
co-deposition of a metal oxide of the metal and silicon, or
co-deposition of a metal oxide of the metal and silicon oxide; and

a tunnel barrier layer of insulating material disposed between the resistive switching layer and the top electrode layer or the bottom electrode layer.

16. The RRAM of claim 15 , wherein a thickness of the bottom electrode is between a range about 5-500 nm.

17. The RRAM of claim 16 , wherein a thickness of the resistive switching layer is between a range about 1-100 nm.

18. The RRAM of claim 17 , wherein a thickness of the top electrode layer is between a range about 5-500 nm.

19. The RRAM of claim 18 , wherein a thickness of the tunnel barrier layer is between a range about 0.5-50 nm.

20. The RRAM of claim 19 , wherein the metal of the resistive switching layer is tungsten.

Assignees

• Chang Ting-Chang
• Syu Yong-En
• Jian Fu-Yen
• Chang Shih-Chieh
• Wang Ying-Lang
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Ting-Chang
• Syu Yong-En
• Jian Fu-Yen
• Chang Shih-Chieh
• Wang Ying-Lang

Classifications

• H01L27/2436

  Electricity · mapped topic

• H01L45/12

  Electricity · mapped topic

• H01L45/04 Primary

  Electricity · mapped topic

• H01L45/145

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic