Oxide semiconductor device

Patent metadata

Field	Value
Publication number	US-9847428-B1
Application number	US-201615230496-A
Country	US
Kind code	B1
Filing date	Aug 8, 2016
Priority date	Aug 8, 2016
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

An oxide semiconductor device includes an oxide semiconductor transistor including a first gate electrode, a second gate electrode, a third gate electrode, a first oxide semiconductor channel layer, a second oxide semiconductor channel layer, and two source/drain electrodes. The second gate electrode is disposed above the first gate electrode. The third gate electrode is disposed above the second gate electrode. At least a part of the first oxide semiconductor channel layer is disposed between the first gate electrode and the second gate electrode. At least a part of the second oxide semiconductor channel layer is disposed between the second gate electrode and the third gate electrode. At least a part of each source/drain electrode is disposed between the first oxide semiconductor channel layer and the second oxide semiconductor channel layer. Each source/drain electrode contacts the first oxide semiconductor channel layer and the second oxide semiconductor channel layer.

First claim

What is claimed is:

1. An oxide semiconductor device, comprising:
an oxide semiconductor transistor, comprising:
a first gate electrode;
a second gate electrode disposed above the first gate electrode;
a third gate electrode disposed above the second gate electrode;
a first oxide semiconductor channel layer, wherein at least a part of the first oxide semiconductor channel layer is disposed between the first gate electrode and the second gate electrode;
a second oxide semiconductor channel layer, wherein at least a part of the second oxide semiconductor channel layer is disposed between the second gate electrode and the third gate electrode;
two source/drain electrodes, wherein at least a part of each of the source/drain electrodes is disposed between the first oxide semiconductor channel layer and the second oxide semiconductor channel layer, and each of the source/drain electrodes physically contacts the first oxide semiconductor channel layer and the second oxide semiconductor channel layer; and
two auxiliary electrodes, wherein each of the auxiliary electrodes is disposed on the second oxide semiconductor channel layer and one of the source/drain electrodes, and each of the auxiliary electrodes contacts and is electrically connected to the corresponding source/drain electrode.

2. The oxide semiconductor device of claim 1 , wherein the oxide semiconductor transistor further comprises:
a first gate insulation layer disposed between the first oxide semiconductor channel layer and the first gate electrode;
a second gate insulation layer disposed between the first oxide semiconductor channel layer and the second gate electrode;
a third gate insulation layer disposed between the second gate electrode and the second oxide semiconductor channel layer; and
a fourth gate insulation layer disposed between the second oxide semiconductor channel layer and the third gate electrode.

3. The oxide semiconductor device of claim 2 , wherein the oxide semiconductor transistor further comprises:
a first interface layer disposed between the first gate insulation layer and the first oxide semiconductor channel layer, wherein a lattice mismatch between the first interface layer and the first oxide semiconductor channel layer is lower than a lattice mismatch between the first gate insulation layer and the first oxide semiconductor channel layer.

4. The oxide semiconductor device of claim 2 , wherein the oxide semiconductor transistor further comprises:
a second interface layer disposed between the fourth gate insulation layer and the second oxide semiconductor channel layer, wherein a lattice mismatch between the second interface layer and the second oxide semiconductor channel layer is lower than a lattice mismatch between the fourth gate insulation layer and the second oxide semiconductor channel layer.

5. The oxide semiconductor device of claim 2 , wherein the first oxide semiconductor channel layer is thicker than the first gate insulation layer and the second gate insulation layer.

6. The oxide semiconductor device of claim 2 , wherein the second oxide semiconductor channel layer is thicker than the third gate insulation layer and the fourth gate insulation layer.

7. The oxide semiconductor device of claim 1 , further comprising:
a plurality of contact structures, wherein each of the contact structures penetrates an interlayer dielectric covering at least a part of the oxide semiconductor transistor.

8. The oxide semiconductor device of claim 7 , wherein each of the source/drain electrodes comprises a first part and a second part, a distance between the first part of each of the source/drain electrodes and the second gate electrode is shorter than a distance between the second part of each of the source/drain electrodes and the second gate electrode, and the contact structures are disposed on the second parts of the source/drain electrodes.

9. The oxide semiconductor device of claim 8 , wherein each of the source/drain electrodes covers a side surface of the first oxide semiconductor channel layer, and the second parts of the source/drain electrodes are lower than the first parts of the source/drain electrodes.

10. The oxide semiconductor device of claim 8 , wherein the first parts and the second parts of the source/drain electrodes are disposed on the first oxide semiconductor channel layer.

11. The oxide semiconductor device of claim 1 , further comprising:
a plurality of contact structures, wherein each of the contact structures penetrates an interlayer dielectric covering at least a part of the oxide semiconductor transistor and contacts one of the auxiliary electrodes.

12. The oxide semiconductor device of claim 11 , wherein each of the contact structures is electrically connected to one of the source/drain electrodes via the corresponding auxiliary electrode.

13. The oxide semiconductor device of claim 11 , wherein a part of the second oxide semiconductor channel layer is disposed between the second gate electrode and each of the auxiliary electrodes.

14. The oxide semiconductor device of claim 11 , wherein a part of the second oxide semiconductor channel layer is disposed between each of the auxiliary electrodes and the corresponding source/drain electrode.

Assignees

• United Microelectronics Corp

Inventors

• Zhou Zhibiao
• Chen Ding-Lung

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6734 Primary

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L29/41733

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic