Field effect transistor and method of manufacture

Patent metadata

Field	Value
Publication number	US-9847415-B2
Application number	US-201414523076-A
Country	US
Kind code	B2
Filing date	Oct 24, 2014
Priority date	Apr 8, 2008
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A semiconductor structure and method of manufacture and, more particularly, a field effect transistor that has a body contact and method of manufacturing the same is provided. The structure includes a device having a raised source region of a first conductivity type and an active region below the raised source region extending to a body of the device. The active region has a second conductivity type different than the first conductivity type. A contact region is in electric contact with the active region. The method includes forming a raised source region over an active region of a device and forming a contact region of a same conductivity type as the active region, wherein the active region forms a contact body between the contact region and a body of the device.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a field effect transistor device having a raised source region of a first conductivity type;
an active region below the raised source region extending to a body of the field effect transistor device, the active region having a second conductivity type different than the first conductivity type;
a gate oxide on the active region;
a gate conductor on the gate oxide;
a contact region in electric contact with the active region; and
an etch stop layer on the body of the field effect transistor device and between the raised source region and the contact region of the field effect transistor device,
wherein the active region comprises an underpass connection under the raised source region between the contact region and the body of the field effect transistor device such that the contact region is coupled to the body of the field effect transistor device, and
the raised source region is over sidewalls and a portion of a top surface of the gate conductor.

2. The semiconductor device of claim 1 , wherein the contact region is in electric contact with the body of the field effect transistor device.

3. The semiconductor device of claim 1 , wherein the contact region is of a different conductivity type than the first conductivity type.

4. The semiconductor device of claim 1 , wherein the field effect transistor device further comprises a raised drain region.

5. The semiconductor device of claim 4 , further comprising a silicide metal in contact with the field effect transistor device, the contact region and the raised drain region.

6. The semiconductor device of claim 5 , further comprising metal contacts in electric contact with the silicide metal.

7. The semiconductor device of claim 1 , further comprising a silicide metal in contact with the field effect transistor device, the contact region, the raised source region and a raised drain region.

8. The semiconductor device of claim 7 , further comprising metal contacts in electric contact with the silicide metal.

9. The semiconductor device of claim 7 , wherein the etch stop layer is between the silicide metal of the raised source region and the contact region, thereby forming a symmetric FET with an isolated body contact.

10. The semiconductor device of claim 1 , wherein the active region and the contact region form a symmetric body contact.

11. The semiconductor device of claim 1 , wherein the first conductivity type reaches only partly through the active region below the raised source region.

12. The semiconductor device of claim 1 , wherein the raised source region is approximately 100 nm and prevents a dopant from extending entirely through the underpass connection to a buried oxide layer under the active region.

13. The semiconductor device of claim 1 , further comprising a drain region in a same material which forms the active region.

14. The device of claim 13 , wherein the drain region is a lightly doped drain.

15. The device of claim 13 , wherein the first conductivity type reaches only partly through the active region below the raised source region.

16. The device of claim 13 , further comprising an n-type doped region adjacent to the drain region, on a side opposing the raised source region.

17. The device of claim 16 , further comprising a silicide metal in contact with the device, the contact region, the raised source region and the n-type doped region, and metal contacts in electric contact with the silicide metal.

18. The device of claim 17 , further comprising an isolation structure between the silicide metal of the raised source region and the contact region.

19. The device of claim 1 , wherein the active region is directly on a buried oxide layer, a cap comprising dielectric material is directly on the gate conductor comprising a polysilicon layer, and the raised source region is directly on the cap.

20. The device of claim 19 , wherein a top surface of the contact region is below a bottom surface of the gate oxide, the first conductivity type is n-type dopant, and the second conductivity type is p-type dopant.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Botula Alan B
• Joseph Alvin J
• Luce Stephen E
• Pekarik John J
• Shi Yun

Classifications

• H10D30/608 Primary

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H01L29/0847

  Electricity · mapped topic

• H01L29/7834 Primary

  Electricity · mapped topic

• H01L29/41783

  Electricity · mapped topic

• H01L29/66575

  Electricity · mapped topic