Semiconductor device including an active region and two layers having different stress characteristics

Patent metadata

Field	Value
Publication number	US-9847389-B2
Application number	US-201314063459-A
Country	US
Kind code	B2
Filing date	Oct 25, 2013
Priority date	Dec 20, 2006
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first active region, the first active region including a first channel region, the first channel region having a transverse direction and a lateral direction, wherein current flows through the first channel region in the lateral direction;
a first transistor gate that overlies the first channel region;
a second active region spaced apart from the first active region in the transverse direction, the second active region including a second channel region that is aligned with the first channel region in the transverse direction;
an isolation region between the first active region and the second active region,
wherein the isolation region includes a first region that is located between the first channel region and the second channel region;
wherein the isolation region further includes a second region that is located in the lateral direction from the first region;

a dummy structure that overlies the second region of the isolation region, the dummy structure comprising a same gate material as that of the first transistor gate, the dummy structure offset from the first transistor gate by an offset distance in the lateral direction; and
a first layer located over the first region of the isolation region and the second region of the isolation region, wherein the first layer is separated from the first region by a first vertical distance that is less than a second vertical distance between the first layer and the second region, and the first layer is vertically separated from the second region of the isolation region by the dummy structure.

2. The semiconductor device of claim 1 , wherein the first layer includes silicon nitride.

3. The semiconductor device of claim 1 , wherein no dummy structure of gate material is located between the first region and the first layer.

4. The semiconductor device of claim 1 , wherein the first layer is not located over the first active region.

5. The semiconductor device of claim 1 , further comprising: a second transistor gate overlying the second channel region, the second transistor gate aligned with the first transistor gate in the transverse direction.

6. The semiconductor device of claim 1 , wherein the first transistor gate and the dummy structure have a same thickness in a vertical direction.

7. The semiconductor device of claim 1 , wherein the first active region further comprises:
a third channel region parallel to the first channel region, wherein the third channel region is offset from the first channel region in the lateral direction by twice the offset distance between the dummy structure and the first transistor gate.

8. The semiconductor device of claim 7 , wherein the second active region further comprises:
a fourth channel region parallel to the second channel region, the fourth channel region offset from the second channel region in the lateral direction, the fourth channel region aligned with the third channel region of the first active region.

9. The semiconductor device of claim 1 , wherein the first transistor gate has a length defined by a first edge and a second edge, the dummy structure has a length defined by a third edge and a fourth edge, each of the first edge, the second edge, third edge, and the fourth edge extending in the transverse direction, and the first edge and the second edge offset from the third edge and the fourth edge in the lateral direction.

10. The semiconductor device of claim 1 , wherein the dummy structure comprises polysilicon.

11. The semiconductor device of claim 1 , wherein the first active region includes a plurality of channel regions, including the first channel region, spaced apart from each other channel region in the lateral direction.

12. The semiconductor device of claim 1 , wherein
the first layer is further located over the second active region.

13. The semiconductor device of claim 1 , further comprising:
a second layer having a stress type that is opposite to a stress type of the first layer and is located over the first active region.

14. The semiconductor device of claim 13 , wherein the stress type of the first layer is compressive, and the stress type of the second layer is tensile.

15. A semiconductor device comprising:
a first active region, the first active region including a first channel region, the first channel region having a transverse direction and a lateral direction, wherein current flows through the first channel region in the lateral direction, and wherein the first active region also comprises a second channel region parallel to the first channel region, the second channel region is offset from the first channel region by an offset distance in the lateral direction;
a first transistor gate that overlies the first channel region;
a second active region spaced apart from the first active region in the transverse direction;
an isolation region between the first active region and the second active region;
wherein the isolation region includes a first region that is located in the transverse direction from the first channel region;
wherein the isolation region includes a second region that is located in the lateral direction from the first region;

a dummy structure that overlies the second region of the isolation region between the first and second active regions, the dummy structure comprising a same gate material as that of the first transistor gate, the dummy structure offset from the first transistor gate by half of the offset distance in the lateral direction; and
a first layer located over the first region of the isolation region and the second region of the isolation region, wherein the first layer is separated from the first region by a first vertical distance that is less than a second vertical distance between the first layer and the second region, and the first layer is vertically separated from the second region of the isolation region by the dummy structure.

16. The semiconductor device of claim 15 , further comprising:
a second layer having a stress type that is opposite to a stress type of the first layer, the second layer located over the first active region.

17. The semiconductor device of claim 15 , wherein
the first layer is further located over the second active region.

Assignees

• Winstead Brian A
• Adams Vance H
• Grudowski Paul A
• Nxp Usa Inc

Inventors

• Winstead Brian A
• Adams Vance H
• Grudowski Paul A

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H01L29/7842

  Electricity · mapped topic

• H01L29/0642 Primary

  Electricity · mapped topic

• H01L27/1203

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic