Semiconductor devices having air spacers and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9847278-B2
Application number	US-201615095327-A
Country	US
Kind code	B2
Filing date	Apr 11, 2016
Priority date	Aug 31, 2015
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A semiconductor device includes first and second bit line structures on a substrate and spaced apart from each other, a via plug partially filling between the first and second bit line structures, a via pad in contact with an upper surface of the via plug and an upper sidewall of the first bit line structure, the via pad being spaced apart from an upper portion of the second bit line structure, a first cavity filled with air being between the via plug and the first bit line structure and a second cavity filled with air between the via plug and the second bit line structure, A gap capping spacer having a first portion on the upper sidewall of the first bit line structure and a second portion covers the first air spacer. A horizontal width of the first portion is smaller than that of the second portion.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first bit line structure and a second bit line structure on a substrate, the first and second bit line structures being spaced apart from each other;
a via plug partially filling an area between the first bit line structure and the second bit line structure;
a via pad in contact with an upper surface of the via plug and an upper surface of the first bit line structure, the via pad being spaced apart from an upper portion of the second bit line structure, the via plug and the first bit line structure separated from each other by a first cavity filled with air, the via plug and the second bit line structure being separated from each other by a second cavity filled with air;
a gap capping spacer having a first portion on an upper sidewall of the first bit line structure and a second portion covering the first cavity, a horizontal width of the first portion of the gap capping spacer being smaller than a horizontal width of the second portion of the gap capping spacer; and
a pad isolation region between an upper portion of the second bit line structure and the via pad, the pad isolation region vertically overlapping the second cavity.

2. The semiconductor device of claim 1 , wherein
a bottom surface of the pad isolation region defines an upper end portion of the second cavity,
a bottom surface of the gap capping spacer defines an upper end portion of the first cavity, and
the bottom surface of the gap capping spacer is at a higher level than the bottom surface of the pad isolation region.

3. The semiconductor device of claim 1 , wherein the upper surface of the via plug is at a lower level than an upper end of the first cavity and an upper end of the second cavity.

4. The semiconductor device of claim 1 , wherein an area connecting the first portion and the second portion of the gap capping spacer has a round shape or a step shape.

5. The semiconductor device of claim 1 , further comprising:
a first inner spacer between the first bit line structure and the first cavity;
a second inner spacer between the second bit line structure and the second cavity;
a first outer spacer between the via plug and the first cavity; and
a second outer spacer between the via plug and the second cavity.

6. The semiconductor device of claim 5 , wherein
an upper surface of the first outer spacer is at a lower level than the upper surface of the first inner spacer, and
an upper surface of the second outer spacer is at a lower level than the upper surface of the second inner spacer.

7. The semiconductor device of claim 5 , wherein the gap capping spacer, the first and second inner spacers and the first and second outer spacers include a same material.

8. The semiconductor device of claim 5 , wherein an upper surface of the first inner spacer is at a higher level than an upper surface of the second inner spacer.

9. The semiconductor device of claim 5 , wherein
the first and second inner spacers and the first and second outer spacers include a same material, and
the gap capping spacer includes a different material from the first and second inner spacers and the first and second outer spacers.

10. The semiconductor device of claim 9 , wherein
the first and second inner spacers and the first and second outer spacers include silicon nitride, and
the gap capping spacer includes at least one of silicon boronitride (SiBN), aluminum oxide (AlO) and titanium oxide (TiO).

11. A semiconductor device, comprising:
a first bit line structure and a second bit line structure on a substrate, the first and second bit line structures being spaced apart from each other;
a via structure between the first and second bit line structures, the via structure including a via plug and a via pad in contact with an upper surface of the via plug, a first side of the via structure and a lower sidewall of the first bit line structure being separated from each other by a first cavity filled with air, a second side of the via structure and a lower sidewall of the second bit line structure being separated from each other by a second cavity filled with air;
a first inner spacer between the first bit line structure and the first cavity;
a first outer spacer between the via plug and the first cavity;
a second inner spacer between the second bit line structure and the second cavity;
a second outer spacer between the via plug and the second cavity;
a pad isolation region partially extending between the second side of the via structure and an upper sidewall of the second bit line structure, a lower surface of the pad isolation region defining an upper end of the second cavity; and
a gap capping spacer between the first side of the via structure and an upper sidewall of the first bit line structure adjacent to the first side of the via structure, the gap capping spacer including a first portion extending along the upper sidewall of the first bit line structure in a first direction and a second portion extending on the first cavity in a second direction perpendicular to the first direction, a horizontal width of the first portion being smaller than a horizontal width of the second portion.

12. The semiconductor device of claim 11 , wherein
the pad isolation region includes an upper pad isolation region at a higher level than upper surfaces of the first and second bit line structures and a lower pad isolation region between the via structure and the second bit line structure, and
a horizontal width of the upper pad isolation region is smaller than a horizontal width of the lower pad isolation region.

13. The semiconductor device of claim 11 , wherein
the lower surface of the pad isolation region includes a first lower surface in contact with the via structure, a second lower surface in contact with the second bit line structure, and a third lower surface defining an upper end of the second cavity, and
the first lower surface is at a higher level than the second lower surface.

14. The semiconductor device of claim 11 , wherein
the pad isolation region includes a pad isolation trench partially extending between the upper sidewall of the second bit line structure and the second side of the via structure, and
a pad isolation insulator filling the pad isolation trench.

15. The semiconductor device of claim 11 , wherein the gap capping spacer defines an upper end of the first cavity, and the upper end of the first cavity is higher than the upper end of the second cavity.

16. The semiconductor device of claim 11 , wherein the pad isolation region includes a lower portion between the second inner spacer and the second outer spacer.

17. A semiconductor device, comprising:
a first bit line structure and a second bit line structure on a substrate;
a via structure between the first and second bit line structures;
a first spacer structure between the first bit line structure and the via structure, the first spacer structure including a first inner spacer extending along a sidewall of the first bit line structure, a first outer spacer on a first sidewall of the via structure, and a gap capping spacer including a first portion disposed along an upper sidewall of the first inner spacer and a second portion disposed on the first outer spacer;
a first cavity surrounded by the first inner spacer, the first outer spacer, and the gap capping spacer;
a second spacer structure between the second bit line structure and the via structure, the second spacer structure including a second inner spacer extending along a sidewall of the second bit line structure and a se

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyung-Eun
• Kim Yongkwan
• Jang Semyeong
• Choi Jaehyoung
• Hwang Yoosang
• Kim Bong-Soo

Classifications

• H10W20/072 Primary

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title