Method for insulating singulated electronic die

Patent metadata

Field	Value
Publication number	US-9847270-B2
Application number	US-201615165894-A
Country	US
Kind code	B2
Filing date	May 26, 2016
Priority date	Aug 26, 2014
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

In one embodiment, a method of forming an electronic device includes providing a wafer having plurality of die separated by spaces. The method includes plasma singulating the wafer through the spaces to form singulation lines that expose side surfaces of the plurality of die. The method includes forming an insulating layer on the exposed side surfaces. In one embodiment, the steps of singulating and forming the insulating layer are carried out with the wafer mounted to a carrier substrate that supports the wafer and singulated die during both steps.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
providing a semiconductor wafer having a plurality of die formed as a part of the wafer and separated by spaces, wherein the semiconductor wafer has first and second opposing major surfaces;
placing the semiconductor wafer onto a carrier tape;
engaging the semiconductor wafer placed on the carrier tape with a first apparatus configured for singulating the semiconductor wafer;
singulating the semiconductor wafer through the spaces to form singulation lines exposing side surfaces of the plurality of die while the semiconductor wafer placed on the carrier tape is engaged with the first apparatus to provide the plurality of die mounted to the carrier tape; and
forming an insulating layer disposed adjoining the side surfaces of the plurality of die, wherein forming the insulating layer comprises:
forming a first portion of the insulating layer using the first apparatus;
engaging the plurality of die mounted to the carrier tape with a second apparatus that is different than the first apparatus; and
forming a second portion of the insulating layer using the second apparatus with the plurality of die mounted to the carrier tape.

2. The method of claim 1 , wherein:
placing the semiconductor wafer onto the carrier tape comprises placing onto the carrier tape attached to a frame;
singulating the semiconductor wafer includes plasma etching through the spaces to singulate the semiconductor wafer to provide the plurality of die;
forming the first portion of the insulating layer occurs at least in part as part of the plasma etching step; and
forming the insulating layer comprises forming the insulating layer on the side surfaces of the plurality of die while the plurality of die are attached to the carrier tape.

3. The method of claim 1 , wherein forming the insulating layer comprises forming the insulating layer having a thickness greater than about 0.5 microns.

4. The method of 1 , wherein forming the insulating layer comprises forming the insulating layer having a thickness greater than about 0.7 microns.

5. The method of claim 1 , wherein forming the insulating layer comprises forming a polymer layer.

6. The method of claim 5 , wherein forming the polymer layer comprises forming a fluorinated carbon polymer layer.

7. The method of claim 1 further comprising attaching one of the plurality of die to a next level of assembly in an chip level package.

8. The method of claim 7 , wherein attaching the one of the plurality of die comprises solder attaching the one of the plurality of die to the next level of assembly, and wherein the insulating layer is configured to protect the exposed side surfaces from solder used in the solder attaching step.

9. The method of claim 1 , wherein providing the semiconductor wafer comprises providing the plurality of die each having a length less than about 1.6 millimeter (mm) and a width less than about 0.8 mm.

10. The method of claim 1 , wherein forming the insulating layer comprises forming a dielectric layer.

11. The method of claim 10 , wherein forming the dielectric layer comprises forming an oxide layer.

12. A method of forming a semiconductor device comprising:
providing a semiconductor wafer having a plurality of die formed as a part of the semiconductor wafer and separated from each other by spaces;
placing the semiconductor wafer onto a carrier substrate;
plasma etching the semiconductor wafer through the spaces to form singulation lines extending into the semiconductor wafer to form a plurality of singulated die, wherein the step of plasma etching is done in a first apparatus; and
thereafter providing an insulating structure by:
forming a first insulating layer adjoining exposed sidewall surfaces of the plurality of singulated die in the first apparatus; and
forming a second insulating layer adjoining the first insulating layer in a second apparatus different than the first apparatus.

13. The method of claim 12 further comprising attaching one of the plurality of singulated die to a next level of assembly in a chip level package configuration.

14. The method of claim 13 , wherein:
attaching the one of the plurality of singulated die comprises solder attaching the one of the plurality of singulated die to the next level of assembly; and
providing the insulating structure comprises providing the insulating structure having a thickness greater than about 0.5 microns.

15. The method of claim 12 , wherein forming the first insulating layer comprises forming a polymer layer.

16. The method of claim 15 , wherein forming the second insulating layer comprises forming an oxide layer.

17. A method of forming a semiconductor device comprising:
providing a semiconductor wafer having a plurality of die formed as a part of the wafer and separated from each other by spaces;
placing the semiconductor wafer onto a carrier tape attached to a frame;
plasma etching the semiconductor wafer through the spaces to form singulation lines extending into the semiconductor wafer to form a plurality of singulated die, wherein the step of plasma etching is done in a first apparatus; and
thereafter providing an insulating structure while the semiconductor wafer is on the carrier tape by:
forming a first insulating layer adjoining exposed sidewall surfaces of the plurality of singulated die in the first apparatus; and
forming a second insulating layer adjoining the first insulating layer in a second apparatus.

18. The method of claim 17 , wherein providing the insulating structure comprises providing the insulating structure having a thickness greater than about 0.5 microns.

19. The method of claim 17 , wherein forming the first insulating layer comprises forming a polymer layer.

20. The method of claim 17 , wherein forming the second insulating layer comprises forming an oxide layer.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Carney Francis J

Classifications

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10P72/0446

  Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates · CPC title

• H10P54/00 Primary

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title