Multi-bit memory device and on-chip buffered program method thereof

Patent metadata

Field	Value
Publication number	US-9847122-B2
Application number	US-201414451953-A
Country	US
Kind code	B2
Filing date	Aug 5, 2014
Priority date	Aug 9, 2013
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A program method of a multi-bit memory device is provided. First page data is programmed in a first region of a memory cell array. The first page data is stored in a first buffer of a page buffer. Second page data is programmed in the first region of the memory cell array. The second page data is stored in a third buffer of the page buffer. Third page data is stored in the first region of the memory cell array. The second page data stored in the third buffer is transferred to a second buffer of the page buffer and the third page data is stored in the third buffer. The first to third page data stored in page buffer are programmed in a second region of the memory cell array.

First claim

What is claimed is:

1. A program method of a multi-bit memory device, the program method comprising:
programming first page data in a first region of a memory cell array;
after the programming of the first page data, storing the first page data in a first buffer of a page buffer;
after the storing of the first page data, programming second page data in the first region of the memory cell array;
after the programming of the second page data, storing the second page data in a third buffer of the page buffer;
after the storing of the second page data, programming third page data in the first region of the memory cell array;
after programming of the third page data, transferring the second page data stored in the third buffer to a second buffer of the page buffer and then storing the third page data in the third buffer; and
performing, based on the first to third page data stored in the page buffer, a first programming operation on a second region of the memory cell array,
wherein the first region of the memory cell array includes a memory cell configured to store 1-bit data, and
wherein the second region of the memory cell array includes a memory cell configured to store M-bit data, where M is a natural number of 3 or greater.

2. The program method of claim 1 ,
wherein the programming of the first to third page data in the first region of the memory cell array comprises temporarily storing the first to third page data to an input buffer of the page buffer and then transferring the first to third page data stored in the input buffer to the second buffer.

3. The program method of claim 2 ,
wherein the programming of the first to third page data in the first region of the memory cell array further comprises transferring the first to third page data stored in the second buffer to an output buffer of the page buffer and programming the first region of the memory cell array based on the first to third page data transferred to the output buffer.

4. The program method of claim 2 ,
wherein the storing of the first page data in the first buffer comprises transferring the first page data temporarily stored in the input buffer to the first buffer.

5. The program method of claim 2 ,
wherein the storing of the second and third page data in the third buffer comprises transferring the second and third page data temporarily stored in the input buffer to the third buffer, respectively.

6. The program method of claim 1 , further comprising:
after the performing of the first programming operation, performing a second programming operation on the second region of the memory cell array based on the first to third data programmed in the first region of the memory cell array.

7. A memory device comprising:
a memory cell array comprising a first region including memory cells configured to store 1-bit data and a second region including memory cells configured to store M-bit data, where M is a natural number of 3 or greater;
a page buffer; and
control logic configured to program first page data in the first region, store the first page data in a first buffer of the page buffer after the program of the first page data, program second page data in the first region after the store of the first page data, store the second page data in a third buffer of the page buffer after the program of the second page data, program third page data in the first region after the store of the second page data, and then after the program of the third page data, transfer the second page data stored in the third buffer to a second buffer of the page buffer and store the third page data in the third buffer, and perform a first programming operation on the second region based on the first to third page data stored in the page buffer.

8. The memory device of claim 7 , wherein the first programming operation temporarily stores the first to third page data to an input buffer of the page buffer and then transfers the first to third page data stored in the input buffer to the second buffer.

9. The memory device of claim 8 , the first programming operation further transfers the first to third page data stored in the second buffer to an output buffer of the page buffer and programs the first region based on the first to third page data transferred to the output buffer.

10. The memory device of claim 8 , the control logic stores the first page data in the first buffer by transferring the first page data temporarily stored in the input buffer to the first buffer.

11. The memory device of claim 8 , wherein the control logic stores the second and third page data in the third buffer by transferring the second and third page data temporarily stored in the input buffer to the third buffer, respectively.

12. The memory device of claim 7 , wherein the control logic performs a second programming operation on the second region based on the first to third data programmed in the first region, after performing the first programming operation.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Wan-Soo
• Kim Taec-Jun
• Nam Sang-Wook
• Lee Jae-Hwa

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/04

  using variable threshold transistors, e.g. FAMOS · CPC title