Memory package, memory module including the same, and operation method of memory package

Patent metadata

Field	Value
Publication number	US-9847105-B2
Application number	US-201615012845-A
Country	US
Kind code	B2
Filing date	Feb 1, 2016
Priority date	Feb 1, 2016
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.

First claim

What is claimed is:

1. A memory package comprising:
a nonvolatile memory chip;
a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip; and
a logic chip configured to perform a refresh operation on the volatile memory chip in response to a refresh command from an external device and to migrate at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed,
wherein both the refresh operation and migration of at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip occur in response to the refresh command.

2. The memory package of claim 1 , wherein the logic chip performs a migration operation through a separate migration-dedicated channel.

3. The memory package of claim 1 , wherein the nonvolatile memory chip and the volatile memory chip are stacked in a direction perpendicular to the logic chip, and
wherein the nonvolatile memory chip, the volatile memory chip, and the logic chip are connected to each other through a through silicon via.

4. The memory package of claim 3 , wherein the logic chip performs the migration operation through the through silicon via.

5. The memory package of claim 1 , wherein the logic chip determines data, being to be migrated, of data stored in the nonvolatile memory chip.

6. The memory package of claim 5 , wherein the data to be migrated is data of which an access frequency is above a specific level.

7. The memory package of claim 1 , wherein the logic chip comprises:
a nonvolatile memory managing unit configured to perform a garbage collection operation and a wear leveling operation about the nonvolatile memory chip.

8. The memory package of claim 1 , wherein the logic chip comprises:
an address managing unit configured to manage addresses of the nonvolatile memory chip and the volatile memory chip such that data corresponding to an address received from the external device is outputted.

9. The memory package of claim 8 , wherein when data corresponding to the received address is stored in the volatile memory chip, the address managing unit converts the received address such that data stored in the volatile memory chip is outputted.

10. The memory package of claim 1 , wherein when the nonvolatile memory chip is accessed, the logic chip transmits a waiting signal, which is a signal for indicating that the nonvolatile memory chip is ready to be accessed, to the external device.

11. The memory package of claim 1 , wherein the memory package communicates with the external device based on a double data rate (DDR) interface.

12. A memory module comprising:
a memory package comprising a volatile memory chip and a nonvolatile memory chip; and
a random access memory (RAM) control device configured to control the memory package under control of an external device, and to periodically transmit a refresh command to the memory package,
wherein the memory package performs a refresh operation on the volatile memory chip in response to the refresh command, and to migrate at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip during the refresh operation,
wherein both the refresh operation and migration of at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip occur in response to the refresh command.

13. The memory module of claim 12 , wherein the memory package comprises a plurality of data signal lines, and
wherein the memory package exchanges data with the external device through a portion of the data signal lines, and migrates at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip through remaining portion of the data signal lines.

14. The memory module of claim 12 , wherein the memory package further comprises:
a logic chip configured to control the volatile memory chip and the nonvolatile memory chip under control of the RAM control device.

15. The memory module of claim 14 , wherein the volatile memory chip and the nonvolatile memory chip are stacked in a direction perpendicular to the logic chip, and the nonvolatile memory chip, the volatile memory chip, and the logic chip are connected to each other through a through silicon via.

16. The memory module of claim 15 , wherein the memory package migrates at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip through the through silicon via.

17. An operation method of a memory package,
wherein the memory package comprises a volatile memory chip and a nonvolatile memory chip,
the operation method comprising:
receiving a refresh command from an external device; and
in response to the refresh command, migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip upon performing a refresh operation on the volatile memory chip,
wherein both the refresh operation and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip occur in response to the refresh command.

Assignees

• Samsung Electronics Co Ltd
• Samsung Electric

Inventors

• Kim Chankyung
• Kang Uksong
• Kim Nam Sung

Classifications

• G11C5/06 Primary

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G11C5/02 Primary

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title