Processor, accelerator, and direct memory access controller within a processor core that each reads/writes a local synchronization flag area for parallel execution

Patent metadata

Field	Value
Publication number	US-9846673-B2
Application number	US-201214355339-A
Country	US
Kind code	B2
Filing date	Oct 30, 2012
Priority date	Nov 4, 2011
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written; and stores the data subjected to the acceleration processing after completion of the acceleration processing, and further writes a flag indicating the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, read instruction corresponding to a flag in a case where the read instruction is the flag checking instruction and it is confirmed that the flag indicating the completion of the acceleration processing has been written.

First claim

What is claimed is:

1. A processor system comprising:
at least one processor core including
a processor for performing arithmetic processing,
a first memory, and
an accelerator coupled to the processor and the first memory through a coupling network, wherein

the first memory includes:
an instruction area for storing a task to be executed by the processor and the accelerator in advance,
a synchronization flag area for storing a flag used to synchronize an operation of the processor and an operation of the accelerator therebetween, and
a data area for storing data to be processed by the processor and the accelerator and data processed by the processor and the accelerator as processed data,

the accelerator is configured to:
read an instruction included in the task to be executed by the accelerator which is stored in the instruction area when the processor system is booted,
operate in accordance with the instruction read by the accelerator,
start, even when the processor is executing another processing, acceleration processing by reading the data stored in the data area and executing the instruction read by the accelerator corresponding to a flag in a case where the instruction read by the accelerator is a flag checking instruction and it is confirmed by the flag checking instruction that a flag indicating that the processor has completed predetermined processing has been written into the synchronization flag area, and
store data subjected to the acceleration processing into the data area by the instruction read by the accelerator after completion of the acceleration processing, and further write a flag indicating that the completion of the acceleration processing into the synchronization flag area by a flag setting instruction read by the accelerator, and the processor is configured to:
read an instruction included in the task to be executed by the processor which is stored in the instruction area when the processor system is booted
operate in accordance with the instruction read by the processor, and
start, even when the accelerator is executing another processing, the instruction read by the processor corresponding to a flag in a case where the instruction read by the processor is a flag checking instruction and it is confirmed by the flag checking instruction that the flag indicating the completion of the acceleration processing has been written into the synchronization flag area.

2. The processor system according to claim 1 , wherein
each of the accelerator and the processor is configured to write a plurality of different flags corresponding to instructions to be executed subsequently into the synchronization flag area in accordance with progress of processing executed by itself, and
each of the accelerator and the processor for subsequently executing the instructions is configured to confirm the flag written in the synchronization flag area and execute the instruction corresponding to the flag.

3. The processor system according to claim 1 , wherein
the first memory includes at least one of a local memory that is accessible by the accelerator and the processor, and a distributed shared memory that is accessible by another processor core,
the at least one processor core further includes a data transfer unit for transferring data between the first memory and a second memory wherein the second memory is different from the first memory,
the synchronization flag area includes an area for storing a flag used to synchronize an operation of the data transfer unit and operations of the processor and the accelerator therebetween,
the instruction area includes an area for storing a task to be executed by the data transfer unit in advance,
the accelerator is configured to:
start, even when the data transfer unit is executing another data transfer processing, the acceleration processing by reading the data written in the data area and executing the instruction read by the accelerator corresponding to the flag in a case of confirming that a flag indicating that the data transfer unit has completed predetermined data transfer processing has been written into the synchronization flag area, and
store the data subjected to the acceleration processing into the data area after the completion of the acceleration processing, and further write the flag indicating the completion of the acceleration processing into the synchronization flag area, and

the data transfer unit is configured to start, even when the accelerator is executing another processing, data transfer processing by executing the instruction corresponding to the flag in a case of confirming that the flag indicating the completion of the acceleration processing has been written into the synchronization flag area.

4. The processor system according to claim 1 , wherein
the accelerator includes:
a processing part for executing the acceleration processing,
an internal storage area for temporarily storing data processed by the processing part, and
a load/store unit for executing data transfer between the internal storage area and the first memory, and

the load/store unit includes a load/store-unit-side flag writing/confirming unit for writing a flag into the synchronization flag area in accordance with an execution status of the data transfer between the internal storage area and the first memory and confirming that the flag has been written into the synchronization flag area.

5. The processor system according to claim 1 , wherein
the accelerator includes:
a processing part for executing the acceleration processing, and
an internal storage area for temporarily storing data processed by the processing part, and

the processing part includes a processing-part-side flag writing/confirming unit for writing a flag into the synchronization flag area in accordance with an execution status of data transfer between the internal storage area and the processing part and confirming that the flag has been written into the synchronization flag area.

6. The processor system according to claim 1 , wherein
the accelerator includes:
a processing part for executing the acceleration processing,
an internal storage area for temporarily storing data processed by the processing part, and
a load/store unit for executing data transfer between the internal storage area and the first memory,

the processing part includes a processing-part-side flag writing/confirming unit for writing a flag into the synchronization flag area in accordance with an execution status of processing performed by the processing part and confirming that the flag has been written into the synchronization flag area, and
the load/store unit includes a load/store-unit-side flag writing/confirming unit for writing a flag into the synchronization flag area in accordance with the execution status of processing performed by the load/store unit and confirming that the flag has been written into the synchronization flag area.

7. The processor system according to claim 1 , wherein
the accelerator includes:
a processing part for executing the acceleration processing,
an internal storage area for temporarily storing data processed by the processing part,
a load/store unit for executing data transfer between the internal storage area and the first memory, and
a flag exchange register for storing a flag used to synchronize an operation of the processing part and an operation of the load/store unit,

the processing part includes a processing-part-side flag writing/confirming unit for writing a flag into one of the synchronization flag area and the flag exchange register in accordance with an execution status of processing performed by the processing part and confirming that the flag has been written into the one of the synchronization flag

Assignees

• Univ Waseda

Inventors

• Kasahara Hironori
• Kimura Keiji

Classifications

• G06F9/3881

  Arrangements for communication of instructions and data · CPC title

• G06F9/30087

  Synchronisation or serialisation instructions · CPC title

• G06F9/52 Primary

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F15/167

  using a common memory, e.g. mailbox · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title