Method of controlling direct memory access of a peripheral memory of a peripheral by a master, an associated circuitry, an associated device and an associated computer program product

Patent metadata

Field	Value
Publication number	US-9846663-B2
Application number	US-201314778115-A
Country	US
Kind code	B2
Filing date	Mar 22, 2013
Priority date	Mar 22, 2013
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

First claim

The invention claimed is:

1. A method of controlling direct memory access of a peripheral memory of a peripheral by a master, the method comprising:
checking whether there is a pending request from the peripheral for a direct memory access service;
establishing whether an access condition is satisfied in dependence on at least whether there is a pending request;
if the access condition is satisfied, granting access to the master; and
establishing an indicator to indicate that a request is pending upon receiving a request from the peripheral for a direct memory access service and establishing the indicator to indicate that the request is no longer pending upon completion of the direct memory access service,
wherein checking whether there is a pending request from the peripheral for a direct memory access service comprises receiving a request from the peripheral for a direct memory access service and latching the request until a latch reset is performed.

2. A method according to claim 1 , further comprising, if the access condition is not satisfied, denying access to the master.

3. A method according to claim 1 , wherein checking whether there is a pending request from the peripheral for a direct memory access service comprises checking whether the peripheral made a request for the direct memory access service and checking whether the direct memory access service requested by the peripheral has not yet been completed.

4. A method according to claim 1 , further comprising performing the latch reset after an execution of the direct memory access service associated with the request has been completed.

5. A method according to claim 4 , wherein performing the latch reset is performed by the indicator changing from indicating that a request is pending to indicating that the request is no longer pending.

6. A method according to claim 1 , wherein the indicator is established by a direct memory access controller.

7. A method according to claim 1 , the method further comprising: establishing a master ID associated with the master; and comparing the master ID with one or more pre-established master IDs to obtain a master comparison result, the one or more pre-established master IDs indicating masters allowed to access the peripheral, wherein establishing whether the access condition is satisfied is performed in further dependence on at least the master comparison result.

8. A method according to claim 7 , wherein establishing the master ID comprises receiving the master ID from the master.

9. A method according to claim 7 , wherein the master is one of a plurality of bus masters and, if the access condition is satisfied, access is exclusively granted to the master.

10. A circuitry comprising one or more masters; a direct memory access controller; one or more peripherals with associated peripheral memories; and an access control circuitry associated with the one or more peripherals, the direct memory access controller and the access control circuitry being arranged to control direct memory access of a peripheral memory of a peripheral of the one or more peripherals by a master of the one or more masters in dependence on at least a direct memory access request from the peripheral, the control comprising:
checking whether there is a pending request from the peripheral for a direct memory access service,
establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and
if the access condition is satisfied, granting access to the master, the access control circuitry being arranged to, in checking whether there is a pending request from the peripheral for a direct memory access service, check whether the peripheral made a request for the direct memory access service and check whether the direct memory access service requested by the peripheral has not yet been completed, and
the direct memory access controller being arranged to establish an indicator to indicate that a request is pending upon receiving a request from the peripheral for a direct memory access service and establish the indicator to indicate that the request is no longer pending upon completion of the direct memory access service, and the access control circuitry being arranged to receive the indicator for using the indicator to check whether there is a pending request from the peripheral for a direct memory access service.

11. A circuitry according to claim 10 , the direct memory access controller and the access control circuitry arranged to
check whether there is a pending request from the peripheral for a direct memory access service,
establish whether an access condition is satisfied in dependence on at least whether there is a pending request, and
if the access condition is satisfied, grant access to the master.

12. A circuitry according to claim 10 , the access control circuitry comprising a logical AND circuit and a logical NOT circuit, the logical NOT circuit being arranged to receive the indicator as established by the direct memory access controller on its input and to provide an NOT-version of the indicator on its output, and the logical AND circuit being arranged to receive a request from the peripheral for a direct memory access and the NOT-version of the indicator on its inputs so as to obtain an indicator of an active pending request on its output.

13. A circuitry according to claim 10 , the access control circuitry being further arranged to establishing a master ID associated with the master and to compare the master ID with one or more pre-established master IDs to obtain a master comparison result, the one or more pre-established master IDs indicating masters allowed to access the peripheral, wherein establishing whether the access condition is satisfied is performed in further dependence on at least the master comparison result.

14. A device comprising a circuitry according to claim 10 .

15. A device according to claim 14 , the device comprising a microcontroller.

Assignees

• Roberston Alistair
• Culshaw Carl
• Devine Alan
• Nxp Usa Inc

Inventors

• Roberston Alistair
• Culshaw Carl
• Devine Alan

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title