Chained CPP command

Patent metadata

Field	Value
Publication number	US-9846662-B2
Application number	US-201414492015-A
Country	US
Kind code	B2
Filing date	Sep 20, 2014
Priority date	Sep 20, 2014
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A chained Command/Push/Pull (CPP) bus command is output by a first device and is sent from a CPP bus master interface across a set of command conductors of a CPP bus to a second device. The chained CPP command includes a reference value. The second device decodes the command, in response determines a plurality of CPP commands, and outputs the plurality of CPP commands onto the CPP bus. The second device detects when the plurality of CPP commands have been completed, and in response returns the reference value back to the CPP bus master interface of the first device via a set of data conductors of the CPP bus. The reference value indicates to the first device that an overall operation of the chained CPP command has been completed.

First claim

What is claimed is:

1. A method comprising:
(a) receiving a chained command onto a device from a bus, wherein the chained command includes a reference value;
(b) in response to the receiving of the chained command in (a) outputting a plurality of commands onto the bus, wherein each of the commands causes a corresponding amount of data from a first portion of memory to be written into a second portion of memory, wherein due to the outputting of the plurality of commands the data is moved so that the data is stored in the second portion of memory, and wherein the chained command does not include any address; and
(c) outputting the reference value from the device onto the bus, wherein (a) through (c) are performed by the device, and wherein the device includes no processor that fetches and executes processor-executable instructions.

2. The method of claim 1 , wherein the bus is a Command/Push/Pull (CPP) bus, wherein the CPP bus has a set of command conductors, a set of pull-id conductors, and a set of data conductors, wherein the chained command in (a) is received onto the device via the set of command conductors, and wherein the reference value is output from the device in (c) via the set of data conductors.

3. The method of claim 1 , wherein each of the commands output in (b) causes another device to write the corresponding amount of data into the second portion of memory.

4. The method of claim 1 , wherein each of the commands output in (b) causes another device to read the corresponding amount of data from the first portion of memory and to write the corresponding amount of data into the second portion of memory.

5. The method of claim 1 , wherein the plurality of commands in (b) are output onto the bus one by one in a sequence, and wherein one of the plurality of commands is a last command, and wherein the reference value is output in (c) after the last command in (b) has been output onto the bus.

6. The method of claim 1 , wherein the chained command includes an identifier that identifies data to be moved.

7. The method of claim 1 , wherein the device includes a state machine that controls the outputting of each of the commands in (b) and that detects when a write of the corresponding amount of data into the second portion of memory has been initiated.

8. The method of claim 1 , wherein the device includes a state machine that controls the outputting of each of the commands in (b) and that detects when a move of the corresponding amount of data has been completed.

9. The method of claim 1 , wherein the device includes a state machine that monitors how many commands have been output in (b) onto the bus.

10. The method of claim 1 , wherein the device includes a target bus interface through which the chained command is received in (a) from the bus, and wherein the device includes a master bus interface through which the plurality of commands are output in (b) onto the bus.

11. The method of claim 1 , wherein the each of the commands that is output in (b) onto the bus is a command to another device.

12. The method of claim 1 , wherein the chained command does not include any memory address, wherein the chained command causes the device to obtain a memory address, and wherein the device uses the memory address to cause data to be read from the first portion of memory.

13. The method of claim 1 , wherein the chained command does not include any memory address, wherein the chained command causes the device to obtain a memory address, and wherein the device uses the memory address to cause data to be written into the second portion of memory.

14. The method of claim 1 , wherein the data is moved in (b) so that the data is stored in contiguous memory locations in the second portion of memory.

15. An apparatus comprising:
a first portion of memory;
a second portion of memory;
a Command/Push/Pull (CPP) bus, wherein the CPP bus includes a set of command conductors, a set of pull-id conductors, and a set of data conductors; and
means for: 1) receiving a chained command from the CPP bus via the command conductors, wherein the chained command includes a reference value, and wherein the chained command does not include any address, 2) in response to the receiving of the chained command outputting a plurality of commands onto the CPP bus, wherein each of the commands causes a corresponding amount of data from the first portion of memory to be written into the second portion of memory, wherein due to the outputting of the plurality of commands the data is moved so that the data is stored in the second portion of memory, and 3) outputting the reference value onto the data conductors of the CPP bus, wherein the means includes no processor that fetches and executes processor-executable instructions, and wherein the chained command includes an identifier that identifies data to be moved.

16. The apparatus of claim 15 , wherein the means comprises a state machine, a command decoder, a CPP bus target interface, and a CPP bus master interface.

17. The apparatus of claim 15 , wherein the means receives the chained command via the set of command conductors of the CPP bus, and wherein means outputs the reference value onto the data conductors of the CPP bus.

18. The apparatus of claim 15 , wherein the outputting of the plurality of commands by the means causes the data to be moved across the CPP bus from the first portion of memory to the second portion of memory.

19. The apparatus of claim 15 , wherein the means is also for controlling the outputting of each of the commands and for detecting when a write of the corresponding amount of data into the second portion of memory has been initiated.

20. The apparatus of claim 15 , wherein the means is also for controlling the outputting of each of the commands and for detecting when a write of the corresponding amount of data into the second portion of memory has been completed.

Assignees

• Netronome Systems Inc

Inventors

• Mirza Salma
• Stark Gavin J

Classifications

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/1642

  with request queuing · CPC title