Controlling power consumption in multi-core environments

Patent metadata

Field	Value
Publication number	US-9846475-B2
Application number	US-201213977525-A
Country	US
Kind code	B2
Filing date	Mar 31, 2012
Priority date	Mar 31, 2012
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

Systems and methods of enabling modulation of a frequency of a first core in a multi-core environment include logic to determine a power limit assigned to the first core, logic to determine a stall count of the first core, and logic to modulate the frequency of the first core based at least on the power limit assigned to the first core and the stall count of the first core. The first core is included in a first tile of a socket in the multi-core computer environment.

First claim

I claim:

1. An apparatus comprising:
logic to determine a power limit assigned to a first core;
logic to determine stall count of the first core, wherein the first core is not to perform any instruction when the core is stalled; and
logic to modulate a frequency of the first core based at least on the power limit assigned to the first core and the stall count of the first core, wherein the frequency of the first core is to be decreased when the stall count is higher than a threshold, and wherein the first core is to be included in a first tile of a socket in a multi-core computer environment.

2. The apparatus of claim 1 , further comprising:
logic to determine an estimated power requirement of the first core, wherein the frequency of the first core is to be modulated further based on the estimated power requirement of the first core.

3. The apparatus of claim 2 , wherein the frequency of the first core is to be decreased when the estimated power requirement is less than the power limit.

4. The apparatus of claim 2 , wherein the frequency of the first core is modulated proportionally to a core stall ratio.

5. The apparatus of claim 2 , wherein the frequency of the first core is modulated within a boundary of the power limit.

6. The apparatus of claim 2 , wherein the estimated power requirement of the first core is determined by a core energy monitor of a core local power unit (CLPU) associated with the first core.

7. The apparatus of claim 2 , wherein the power limit is to be assigned to the first core by a power control unit (PCU) associated with the socket.

8. The apparatus of claim 7 , further comprising logic to determine a thermal limit assigned to the first core by the PCU.

9. The apparatus of claim 8 , wherein the frequency of the first core is to be modulated based on the thermal limit.

10. The apparatus of claim 1 , wherein the logic to modulate the frequency of the first core is coupled with a phase locked loop (PLL) associated with the socket.

11. The apparatus of claim 10 , wherein the socket is to be configured to include the first tile and a second tile, and wherein the first tile and the second tile are to be associated with the PLL.

12. The apparatus of claim 11 , wherein the frequency of the first core is to be modulated independently of a frequency associated with the second tile.

13. The apparatus of claim 11 , wherein the first tile is to include the first core and a second core, and wherein the frequency of the first core is to be modulated independently of a frequency associated with the second core.

14. A computer-implemented method comprising:
modulating a frequency of a core in a first tile of a multi-core environment at least independently of cores in other tiles based at least on an estimated power requirement of the core, a power limit assigned to the core and a stall count of the core, wherein the first core is not to perform any instruction when the core is stalled, wherein the frequency of the first core is decreased when the stall count is higher than a threshold, and wherein the first tile and the other tiles are associated with a phase locked loop (PLL) of a socket.

15. The method of claim 14 , further comprising:
determining the estimated power requirement of the core;
determining the power limit assigned to the core; and
determining the stall count of the core.

16. The method of claim 15 , wherein modulating the frequency of the core in the first tile includes decreasing the frequency of the core when the estimated power requirement is less than the power limit.

17. The method of claim 15 , wherein the frequency of the core is modulated proportionally to a core stall ratio.

18. The method of claim 17 , wherein the frequency of the core is modulated within a boundary of the power limit.

19. The method of claim 14 , wherein the estimated power requirement of the core is determined by a core energy monitor of a core local power unit (CLPU) associated with the core.

20. The method of claim 14 , wherein the frequency of the core in the first tile is modulated independently of another core in the first tile.

21. The method of claim 14 , wherein the frequency of the core in the first tile is decreased when the estimated power requirement is less than the power limit.

22. The method of claim 14 , wherein the frequency of the core is modulated proportionally to a core stall ratio.

23. The method of claim 14 , wherein the frequency of the core is modulated within a boundary of the power limit.

24. A system comprising:
a phase locked loop (PLL) configured to be associated with a clock signal in a multi-core environment;
a socket coupled with the PLL and configured to include multiple tiles, at least one of the tiles including a first core and a second core, wherein the first core is configured to include logic to:
determine a power limit assigned to a first core;
determine a stall count of the first core, wherein the first core is not to perform any instruction when the core is stalled; and
modulate a frequency of the first core based at least on the power limit assigned to the first core and the stall count of the first core independently of a frequency of tiles not associated with the first core, wherein the frequency of the first core is to be decreased when the stall count is higher than a threshold.

25. The system of claim 24 , wherein the first core is further configured to include logic to determine an estimated power requirement of the first core.

26. The system of claim 25 , wherein the frequency of the first core is to be modulated based on the estimated power requirement of the first core.

27. The system of claim 25 , wherein the frequency of the first core is to be modulated based on a comparison between the power limit assigned to the first core and the estimated power requirement of the first core.

28. The system of claim 24 , wherein the frequency of the first core is to be modulated independently of a frequency of the second core.

Assignees

• Kumar Anil K
• Intel Corp

Inventors

• Kumar Anil K

Classifications

• Y02B60/1217

  Cross-Sectional Technologies · mapped topic

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• Y02B60/1285

  Cross-Sectional Technologies · mapped topic

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/206

  comprising thermal management · CPC title