Decoupling capacitive arrangement to manage power integrity

Patent metadata

Field	Value
Publication number	US-9844135-B2
Application number	US-201414480430-A
Country	US
Kind code	B2
Filing date	Sep 8, 2014
Priority date	Sep 8, 2014
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

First claim

What is claimed is:

1. A capacitive decoupling arrangement comprising:
a substrate having first and second planar surfaces;
an array of electrical vias extending from the first planar surface of the substrate to the second planar surface of the substrate, the array of electrical vias including a first type of vias and a second type of vias, wherein the first type of vias and the second type of vias are arranged in an alternating rectangular pattern, wherein the first type of vias is associated with a first voltage level and the second type of vias is associated with a second voltage level; and
a capacitive arrangement coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate, the capacitive arrangement including
a first set of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and one of the second type of vias, and
a second set of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and another one of the second type of vias.

2. The capacitive decoupling arrangement of claim 1 , wherein the capacitive arrangement includes a common electrical node that is coupled to the two respective vias of the second type of vias.

3. The capacitive decoupling arrangement of claim 2 , wherein the common electrical node includes two external terminals, each of the two external terminals coupled to a corresponding one of the two respective vias of the second type of vias.

4. The capacitive decoupling arrangement of claim 1 , wherein the capacitive arrangement includes at least four capacitive elements electrically coupled in parallel.

5. The capacitive decoupling arrangement of claim 4 , wherein a first of the at least four capacitive elements is coupled to a first external terminal and a first portion of a common electrical node, a second of the at least four capacitive elements is coupled to the first external terminal and a second portion of a common electrical node, wherein the common electrical node is coupled to the two respective vias of the second type of vias through at least one second external terminal.

6. The capacitive decoupling arrangement of claim 5 , wherein a third of the at least four capacitive elements is coupled to a third external terminal and the first portion of the common electrical node, a fourth of the at least four capacitive elements is coupled to the third external terminal and the second portion of a common electrical node.

7. The capacitive decoupling arrangement of claim 4 , wherein the at least four capacitive elements are included in a single discrete component.

8. The capacitive decoupling arrangement of claim 1 , wherein the capacitive arrangement includes a combination of two or more two-terminal capacitors.

9. The capacitive decoupling arrangement of claim 1 , wherein the array of electrical vias includes at least two of the first type of vias, and at least two of the second type of vias.

10. The capacitive decoupling arrangement of claim 1 , wherein a first one of the first type of vias is adjacent to a first one of the second type of vias in a first direction, adjacent to a second one of the second type of vias in a second direction perpendicular to the first direction, and adjacent to a second one of the first type of vias in a third direction different from first direction and the second direction.

11. The capacitive decoupling arrangement of claim 1 , further comprising an integrated circuit die arranged on the second planar surface of the substrate.

12. The capacitive decoupling arrangement of claim 1 , wherein the first voltage level corresponds with a power supply voltage level coupled to the first type of vias, and the second voltage level corresponds with a ground voltage level.

13. The capacitive decoupling arrangement of claim 1 , wherein the substrate is a printed circuit board.

14. A capacitive decoupling arrangement comprising:
a substrate having first and second planar surfaces;
an array of electrical vias extending from the first planar surface of the substrate to the second planar surface of the substrate, the array of electrical vias including a first type of vias and a second type of vias, wherein the first type of vias and the second type of vias are arranged in an alternating rectangular pattern, wherein the first type of vias is associated with a first voltage level and the second type of vias is associated with a second voltage level; and
a capacitive arrangement coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate, the capacitive arrangement being in the form of a three-terminal capacitor having a first terminal coupled to a first one of the two respective vias of the first type of vias, a second terminal coupled to both of the two respective via of the second type of vias, and a third terminal coupled to second one of the two respective vias of the first type of vias.

15. The capacitive decoupling arrangement of claim 14 , wherein the capacitive arrangement include at least four capacitive elements electrically coupled in parallel.

16. The capacitive decoupling arrangement of claim 15 , wherein a first of the at least four capacitive elements is coupled to a first external terminal and a first portion of a common electrical node, a second of the at least four capacitive elements is coupled to the first external terminal and a second portion of a common electrical node, wherein the common electrical node is coupled to the two respective vias of the second type of vias through at least one second external terminal.

17. The capacitive decoupling arrangement of claim 16 , wherein a third of the at least four capacitive elements is coupled to a third external terminal and the first portion of the common electrical node, a fourth of the at least four capacitive elements is coupled to the third external terminal and the second portion of a common electrical node.

18. The capacitive decoupling arrangement of claim 15 , wherein the at least four capacitive elements are included in a single discrete component.

19. The capacitive decoupling arrangement of claim 14 , wherein the capacitive arrangement include a combination of two or more two-terminal capacitors.

20. The capacitive decoupling arrangement of claim 14 , wherein the array of electrical vias includes at least two of the first type of vias, and at least two of the second type of vias.

Assignees

• Cisco Tech Inc

Inventors

• Wu Feng
• Ji Yongchao
• Tang Yang
• Scearce Stephen
• Liu Shunjia
• Tang Shaochun

Classifications

• H05K1/114

  Pad being close to via, but not surrounding the via · CPC title

• H05K1/113

  Via provided in pad; Pad over filled via · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• H05K2201/10674

  Flip chip · CPC title

• H05K3/3415

  on both sides of the substrate or combined with lead-in-hole components · CPC title