Global shutter pixel with hybrid transfer storage gate-storage diode storage node

US9843754B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9843754-B1
Application numberUS-201615181819-A
CountryUS
Kind codeB1
Filing dateJun 14, 2016
Priority dateJun 14, 2016
Publication dateDec 12, 2017
Grant dateDec 12, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

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An image sensor pixel having a hybrid transfer storage gate-storage diode storage node is disclosed herein. An example image sensor includes a photodiode, a storage diode, a transfer gate, and a buried storage well. The photodiode, storage diode, and buried storage well are all disposed in a semiconductor material. The transfer storage gate may be disposed on a surface of the semiconductor material between the photodiode and the storage diode. Further, the buried storage well may be disposed under the storage diode and partially under the transfer storage gate. Additionally, a length of the transfer storage gate and a length of the storage diode may be equal, and the storage diode may passivate a surface of the semiconductor material between the transfer storage gate and an output gate.

First claim

Opening claim text (preview).

What is claimed is: 1. An image sensor pixel, comprising: a photodiode disposed in a semiconductor material; a storage diode disposed in the semiconductor material; a transfer storage gate disposed on a surface of the semiconductor material between the photodiode and the storage diode; a buried storage well disposed in the semiconductor material, wherein the buried storage well is disposed under the storage diode and partially under the transfer storage gate, wherein a length of the transfer storage gate and a length of the storage diode is equal, and wherein the storage diode passivates a surface of the semiconductor material between the transfer storage gate and an output gate. 2. The image sensor pixel of claim 1 , wherein a combination of the transfer storage gate and the storage diode form a storage node. 3. The image sensor pixel of claim 2 , wherein a charge storage capacity of the storage node is at least equal to a charge storage capacity of the photodiode. 4. The image sensor pixel of claim 3 , wherein the charge storage capacity of the storage node is a combination of a charge storage capacity of the storage diode and a charge storage capacity of the storage well. 5. The image sensor pixel of claim 1 , wherein a charge energy barrier between the photodiode and the storage diode is reduced in response to the length of the transfer storage gate. 6. The image sensor pixel of claim 1 , wherein lengths of the transfer storage gate and the storage diode are optimized to eliminate ghosting. 7. The image sensor pixel of claim 1 , wherein a moderate P dopant implant at the surface of the semiconductor material between the transfer storage gate and an output gate passivates the surface of the semiconductor at an oxide-semiconductor interface. 8. An imaging system, comprising: a pixel array having a plurality of pixels formed in a semiconductor material, the pixel array, in response to a global shutter signal, to simultaneously enable the pixels within the pixel array to simultaneously generate image charge in response to image light, wherein each pixel of the plurality of pixels includes: a photodiode to capture the image light and generate the image charge, the photodiode formed in the semiconductor material and having a photodiode charge storage capacity; a storage node coupled to store the image charge, the storage node formed in the semiconductor material and having a storage node charge storage capacity, wherein the storage node passivates a surface of the semiconductor material to reduce dark current; a transfer storage gate coupled to transfer the image charge from the photodiode to the storage node in response to being activated, the transfer storage gate disposed on the surface of the semiconductor material and formed between the photodiode and the storage node, wherein at least a portion of the transfer storage gate is part of the storage node; a floating diffusion to receive the image charge, the floating diffusion disposed in the semiconductor material; and an output gate coupled to transfer the image charge from the storage node to the floating diffusion, the output gate disposed on the surface of the semiconductor material and formed between the storage node and the floating diffusion; and control circuitry coupled to the pixel array, the control circuitry to provide the global shutter signal. 9. The imaging system of claim 8 , wherein the storage node includes a storage diode and a buried storage well, the storage diode disposed in the semiconductor material between the transfer storage gate and the output gate, and the buried storage well disposed in the semiconductor material under the storage diode and partially under the transfer storage gate. 10. The imaging system of claim 9 , wherein the storage node charge capacity includes a storage capacity of the storage diode and a storage capacity of the buried storage well. 11. The imaging system of claim 9 , wherein a moderate P dopant implant that forms a top layer of the storage diode passivates the surface of the semiconductor material at an oxide-semiconductor interface. 12. The imaging system of claim 8 , wherein the storage node charge storage capacity is substantially equal to the photodiode charge storage capacity. 13. The imaging system of claim 8 , wherein a length of the transfer storage gate is substantially equal to a length of a storage diode portion of the storage node, and wherein the storage node charge storage capacity is at least due to the lengths of the transfer storage gate and the storage diode portion of the storage node. 14. The imaging system of claim 8 , wherein ghosting is eliminated partially in response to a size of the storage node. 15. An image sensor pixel, comprising: a photodiode for generating image charge in response to image light; a storage diode; a buried storage well disposed below the storage diode; a transfer storage gate coupled to transfer the image charge from the photodiode to the buried storage well and the storage diode, wherein the buried storage well is disposed under the storage diode and a portion of the transfer storage gate, and wherein a length of the transfer storage gate is equal to a length of the storage diode; a floating diffusion; and an output gate coupled to transfer the image charge from the buried storage well and the storage diode to the floating diffusion. 16. The image sensor pixel of claim 15 , wherein the storage diode includes two differently doped regions, with a first of the two regions close to a surface of a semiconductor material, wherein the first of the two regions is doped higher than a second of the two regions, and wherein the doping of the first region passivates the surface of the semiconductor material. 17. The image sensor pixel of claim 15 , further comprising an isolation well disposed below the buried storage well. 18. The image sensor pixel of claim 15 , further comprising a global shutter gate coupled to selectively reset the photodiode. 19. The image sensor pixel of claim 15 , wherein relative lengths of the transfer storage gate and the storage diode are optimized to eliminate ghosting. 20. The image sensor pixel of claim 15 , wherein ghosting effects are reduced due to a charge pumping capability of the transfer storage gate.

Assignees

Inventors

Classifications

  • H04N25/626Primary

    Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages · CPC title

  • applied to dark current · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

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What does patent US9843754B1 cover?
An image sensor pixel having a hybrid transfer storage gate-storage diode storage node is disclosed herein. An example image sensor includes a photodiode, a storage diode, a transfer gate, and a buried storage well. The photodiode, storage diode, and buried storage well are all disposed in a semiconductor material. The transfer storage gate may be disposed on a surface of the semiconductor mate…
Who is the assignee on this patent?
Omnivision Tech Inc
What technology area does this patent fall under?
Primary CPC classification H04N25/626. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).