Solid-state image sensor and camera system

US9843747B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9843747-B2
Application numberUS-201615238154-A
CountryUS
Kind codeB2
Filing dateAug 16, 2016
Priority dateOct 20, 2011
Publication dateDec 12, 2017
Grant dateDec 12, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

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There is provided a solid-state image sensor including a pixel array unit in which pixels are arrayed, the pixel including a photodiode converting an optical signal into an electrical signal, and a readout unit which reads out an analog image signal from the pixel to a signal line and processes the read out analog pixel signal in a unit of column. The readout unit includes a ΔΣ modulator which has a function to convert the analog pixel signal in to a digital signal, and an amplifier which is arranged on an input side of the ΔΣ modulator and amplifies the analog pixel signal read out to the signal line using a set gain to input the signal to the ΔΣ modulator.

First claim

Opening claim text (preview).

What is claimed is: 1. A solid-state image sensor comprising: a pixel configured to convert light into an analog pixel signal and output the analog pixel signal onto a signal line, the signal line is electrically connected directly to a first terminal of an input capacitance; an amplifier configured to convert the analog pixel signal into an analog amplified signal by amplifying the analog pixel signal, a second terminal of the input capacitance is electrically connected directly to an input terminal of the amplifier; and a converter configured to convert the analog amplified signal into digital data, an output terminal of the amplifier is electrically connected directly to an input terminal of the converter, wherein the converter is an analog-to-digital converter. 2. The solid-state image sensor according to claim 1 , further comprising: a feedback capacitance electrically connected between a gain switch and the input terminal of the terminal of the amplifier. 3. The solid-state image sensor according to claim 2 , wherein the feedback capacitance is a variable capacitance. 4. The solid-state image sensor according to claim 2 , wherein the gain switch is electrically connected between the feedback capacitance and the output terminal of the terminal of the amplifier. 5. The solid-state image sensor according to claim 2 , wherein the gain switch is controllable to electrically disconnect the output terminal of the amplifier from the feedback capacitance and to electrically connect the feedback capacitance directly to the output terminal of the terminal of the amplifier. 6. The solid-state image sensor according to claim 1 , further comprising: an auto-zero switch electrically connected between the output terminal of the amplifier and the input terminal of the terminal of the amplifier. 7. The solid-state image sensor according to claim 6 , wherein the auto-zero switch is controllable to electrically disconnect the output terminal of the amplifier from the input terminal of the terminal of the amplifier and to electrically connect the output terminal of the amplifier directly to the input terminal of the terminal of the amplifier. 8. The solid-state image sensor according to claim 1 , wherein the amplifier is an inverter type amplifier. 9. The solid-state image sensor according to claim 1 , wherein the converter is a ΔΣ converter. 10. The solid-state image sensor according to claim 1 , wherein the converter includes a ΔΣ modulator. 11. The solid-state image sensor according to claim 10 , wherein the ΔΣ modulator is configured to convert the analog amplified signal in to a digital signal. 12. The solid-state image sensor according to claim 11 , wherein the converter includes a decimation filter circuit, the decimation filter circuit is configured to convert the digital signal into the digital data. 13. The solid-state image sensor according to claim 12 , wherein the decimation filter circuit is configured to convert the digital signal of one bit into the digital data of multiple bits. 14. A camera system comprising: the solid-state image sensor according to claim 1 ; and an optical system configured to form a subject image onto the solid-state image sensor.

Assignees

Inventors

Classifications

  • H04N25/616Primary

    involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

  • Addressed sensors, e.g. MOS or CMOS sensors · CPC title

  • Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

  • SSIS architectures; Circuits associated therewith · CPC title

  • Electricity · mapped topic

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What does patent US9843747B2 cover?
There is provided a solid-state image sensor including a pixel array unit in which pixels are arrayed, the pixel including a photodiode converting an optical signal into an electrical signal, and a readout unit which reads out an analog image signal from the pixel to a signal line and processes the read out analog pixel signal in a unit of column. The readout unit includes a ΔΣ modulator which …
Who is the assignee on this patent?
Sony Semiconductor Solutions Corp
What technology area does this patent fall under?
Primary CPC classification H04N25/616. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 12 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).