Compact, low power advanced encryption standard circuit

Patent metadata

Field	Value
Publication number	US-9843441-B2
Application number	US-201314035508-A
Country	US
Kind code	B2
Filing date	Sep 24, 2013
Priority date	Sep 24, 2013
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.

First claim

What is claimed is:

1. An apparatus comprising:
an encryption unit to perform encryption by processing sixteen bytes of data per round according to an Advanced Encryption Standard algorithm, the encryption unit including
substitution box circuitry to perform a substitution operation on one byte per clock cycle,
an exclusive-OR gate to combine one data byte and one key byte per clock cycle to provide to the substitution box circuitry,
a data register to re-order data bytes to perform a shift-row operation and provide four re-ordered data bytes to the exclusive-OR gate per four clock cycles, wherein the data register includes sixteen one-byte registers in series, each of the sixteen one-byte registers fed by one of sixteen three-input multiplexers, each multiplexer having a first multiplexer input to provide a first byte of plain-text data, a second multiplexer input to provide a second byte of sequentially shifted data, and a third multiplexer input to provide a third byte of re-ordered data,
accumulator circuitry to accumulate four bytes and perform a mix-column operation in four clock cycles, and
scaling circuitry to generate a plurality of scaled bytes from a one-byte substitution box output per clock cycle to provide to the accumulator circuitry, wherein generating the plurality of scaled bytes includes multiplying the one-byte substitution box output by a factor of three and multiplying the one-byte substitution box output by a factor of two.

2. The apparatus of claim 1 , wherein the encryption unit also includes a key register to provide four key bytes, corresponding to the four re-ordered data bytes, to the exclusive-OR gate per four clock cycles.

3. The apparatus of claim 2 , wherein the encryption unit also includes key generation circuitry to generate one key byte for a next round per clock cycle.

4. The apparatus of claim 3 , wherein the encryption unit is to alternate sixteen consecutive clock cycles of encryption with sixteen consecutive clock cycles of key generation.

5. The apparatus of claim 4 , wherein the encryption unit also includes a Galois field mapper to map to an extension field and a ground field.

6. The apparatus of claim 5 , wherein the encryption unit is based on an extension field polynomial of x 2 +6x+C.

7. The apparatus of claim 6 , wherein the encryption unit is based on a ground field polynomial of x 4 +x 3 +1.

8. A method comprising:
performing, with substitution box circuitry, a substitution operation of an Advanced Encryption Standard (AES) algorithm on one substitution box input byte per clock cycle,
performing an exclusive-OR operation to combine one data byte and one key byte per clock cycle to provide to the substitution operation,
re-ordering data bytes to perform a shift-row operation and provide four re-ordered data bytes to the exclusive-OR operation per four clock cycles, wherein the re-ordering is performed by a data register having sixteen one-byte registers in series, each of the sixteen one-byte registers fed by one of sixteen three-input multiplexers, each multiplexer having a first multiplexer input to provide a first byte of plain-text data, a second multiplexer input to provide a second byte of sequentially shifted data, and a third multiplexer input to provide a third byte of re-ordered data,
generating, with scaling circuitry a plurality of scaled bytes from a one-byte substitution box output per clock cycle, wherein generating the plurality of scaled bytes includes multiplying the one-byte substitution box output by a factor of three and multiplying the one-byte substitution box output by a factor of two, and
accumulating, using accumulator circuitry receiving the plurality of scaled bytes, four accumulator input bytes in four clock cycles to perform a mix-column operation of the AES algorithm.

9. The method of claim 8 , further comprising providing four key bytes, corresponding to the four re-ordered data bytes, to the exclusive-OR operation per four clock cycles.

10. The method of claim 9 , further comprising generating one key byte for a next round per clock cycle.

11. The method of claim 10 , further comprising alternating sixteen consecutive clock cycles of encryption with sixteen consecutive clock cycles of key generation.

12. The method of claim 11 , further comprising Galois field mapping to an extension field based on x 2 +6x+C and a ground field based on x 4 +x 3 +1.

13. A system comprising:
a processor including
an encryption unit to generate cipher-text from plain-text according to an Advanced Encryption Standard algorithm, the encryption unit including substitution box circuitry to perform a substitution operation on one byte per clock cycle, an exclusive-OR gate to combine one data byte and one key byte per clock cycle to provide to the substitution box circuitry, a data register to re-order data bytes to perform a shift-row operation and provide four re-ordered data bytes to the exclusive-OR gate per four clock cycles, wherein the data register includes sixteen one-byte registers in series, each of the sixteen one-byte registers fed by one of sixteen three-input multiplexers, each multiplexer having a first multiplexer input to provide a first byte of plain-text data, a second multiplexer input to provide a second byte of sequentially shifted data, and a third multiplexer input to provide a third byte of re-ordered data, accumulator circuitry to accumulate four bytes and perform a mix-column operation in four clock cycles, and scaling circuitry to generate a plurality of scaled bytes from a one-byte substitution box output per clock cycle to provide to the accumulator circuitry, wherein generating the plurality of scaled bytes includes multiplying the one-byte substitution box output by a factor of three and multiplying the one-byte substitution box output by a factor of two; and

a memory to store the cipher-text.

14. A method comprising:
developing a hardware description language model for an encryption unit that performs an Advanced Encryption Standard (AES) algorithm and that includes an eight-bit datapath having a single substitution box to perform a substitution operation on one byte per clock cycle, an exclusive-OR gate to combine one data byte and one key byte per clock cycle to provide to the single substitution box, a data register to re-order data bytes to perform a shift-row operation and provide four reordered data bytes to the exclusive-OR gate per four clock cycles, wherein the data register includes sixteen one-byte registers in series, each of the sixteen one-byte registers fed by one of sixteen three-input multiplexers, each multiplexer having a first multiplexer input to provide a first byte of plain-text data, a second multiplexer input to provide a second byte of sequentially shifted data, and a third multiplexer input to provide a third byte of re-ordered data, and scaling circuitry to generate a plurality of scaled bytes from a one-byte substitution box output per clock cycle to provide to accumulator circuitry, wherein generating the plurality of scaled bytes includes multiplying the one-byte substitution box output by a factor of three and multiplying the one-byte substitution box output by a factor of two;
developing a plurality of parameter files, each parameter file for one of a plurality of a plurality of polynomial pairs for Galois field mapping;
simulating the operation of the encryption unit using the plurality of parameter files to determine the optimum polynomial pair for minimum area of the encryption unit meeting timing and design rule constraints.

Assignees

• Intel Corp

Inventors

• Mathew Sanu
• Suresh Vikram
• Satpathy Sudhir
• Anders Mark
• Kaul Himanshu
• Krishnamurthy Ram

Classifications

• H04L2209/24

  Key scheduling, i.e. generating round keys or sub-keys for block encryption · CPC title

• H04L9/0631 Primary

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title