PSOC architecture

Patent metadata

Field	Value
Publication number	US-9843327-B1
Application number	US-201414283888-A
Country	US
Kind code	B1
Filing date	May 21, 2014
Priority date	Oct 26, 2000
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A circuit with a plurality of analog circuit blocks, each configured to provide at least one analog function and a programmable interconnect coupled of the analog circuit blocks and configurable to interconnect combinations of the analog circuit blocks to one another. The circuit is formed in an integrated circuit (chip) and the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the chip.

First claim

What is claimed is:

1. A circuit comprising:
an IO port;
a plurality of analog circuit blocks comprising:
a first analog circuit block programmable to perform a first function when configured in a first configuration and a second function when configured in a second configuration;
a second analog circuit block programmable to perform a third function when configured in a third configuration and a fourth function when configured in a fourth configuration;
a third analog circuit block programmable to perform a fifth function when configured in a fifth configuration and a sixth function when configured in a sixth configuration;
wherein each of the plurality of analog circuit blocks comprises an input; and

a programmable interconnect structure coupled to each of the plurality of analog circuit blocks and the IO port, configured to couple at least the input of each of the plurality of analog circuit blocks to each other and to the IO port,
wherein the configuration of each of the plurality of analog circuit blocks and of the programmable interconnect structure is programmable during operation.

2. The circuit of claim 1 , wherein at least two of the first function, the third function, and the fifth function together comprise at least part of a complex analog function.

3. The circuit of claim 1 , wherein at least one of the plurality of analog circuit blocks is of a type selected from the group consisting of a continuous time circuit block and a switched capacitor circuit block.

4. The circuit of claim 1 , wherein at least one of the plurality of analog circuit blocks has a fixed function with programmable parameters.

5. The circuit of claim 1 , wherein the IO port comprises a plurality of pins each programmable in accordance with data stored in memory to perform at least one of an input pin function and an output pin function.

6. The circuit of claim 1 , further comprising an internal bus coupling the plurality of analog circuit blocks to the programmable interconnect structure, over which programming information is transferred to configure the function of the plurality of analog circuit blocks and the programmable interconnect structure.

7. The circuit of claim 1 , wherein the configuration of at least one of the programmable interconnect structure, the first analog circuit block, the second analog circuit block, and the third analog circuit block is configurable according to dynamically programmable configuration data.

8. The circuit of claim 1 , further comprising a plurality of programmable digital circuit blocks coupled to the IO port and the first analog circuit block by the programmable interconnect structure.

9. A method comprising:
configuring a first analog circuit block comprising a first input to perform a first function in accordance with dynamically programmable configuration data;
configuring a second analog circuit block comprising a second input to perform a second function in accordance with dynamically programmable configuration data;
configuring a third analog circuit block comprising a third input to perform a third function in accordance with dynamically programmable configuration data; and
configuring a programmable interconnect structure to couple together at least an IO port, the first input, the second input, and the third input in accordance with dynamically programmable configuration data.

10. The method of claim 9 further comprising:
dynamically reconfiguring the first analog circuit block to perform a fourth function in accordance with the dynamically programmable configuration data;
dynamically reconfiguring the second analog circuit block to perform a fifth function in accordance with the dynamically programmable configuration data; and
dynamically reconfiguring the third analog circuit block to perform a sixth function in accordance with the dynamically programmable configuration data.

11. The method of claim 9 , wherein programming the first analog circuit block to perform the first function and programming the second analog circuit block to perform the second function comprises programming the first and second analog circuit blocks in combination to implement at least part of a complex analog function.

12. The method of claim 9 , further comprising configuring the programmable interconnect structure to couple at least one of the IO port and the first analog circuit block to the third analog circuit block, the third analog circuit block having a fixed function with programmable parameters.

13. The method of claim 9 , further comprising configuring each pin of the IO port in accordance with data stored in memory to perform at least one of an input pin function and an output pin function.

14. The method of claim 9 , wherein programming the programmable interconnect structure comprises transferring programming data over an internal bus coupled to the programmable interconnect structure.

15. The method of claim 9 , further comprising configuring a digital circuit block coupled to the IO port and the programmable interconnect structure to perform a seventh function in accordance with dynamically programmable configuration data.

16. A method comprising:
providing an IO port;
providing a plurality of analog circuit blocks comprising:
a first analog circuit block programmable to perform a first function when configured in a first configuration and a second function when configured in a second configuration;
a second analog circuit block programmable to perform a third function when configured in a third configuration and a fourth function when configured in a fourth configuration; and
a third analog circuit block programmable to perform a fifth function when configured in a fifth configuration and a sixth function when configured in a sixth configuration;
wherein each of the plurality of analog circuit blocks comprises an input;

providing a programmable interconnect structure coupled to the plurality of analog circuit blocks and the IO port, and configured to couple at least the input of each of the plurality of analog circuit blocks to each other and to the IO port; and
configuring the plurality of analog circuit blocks and the programmable interconnect structure in accordance with dynamically programmable configuration data.

17. The method of claim 16 , wherein the third analog circuit block has a fixed function with programmable parameters.

18. The method of claim 16 , further comprising configuring each pin of the IO port in accordance with data stored in memory to perform at least one of an input pin function and an output pin function.

19. The method of claim 16 , further comprising:
providing an internal bus coupling plurality of analog circuit blocks and the programmable interconnect structure; and
transferring programming information over the internal bus to configure the function of the plurality of analog circuit blocks and the programmable interconnect structure.

20. The method of claim 16 , further comprising providing a plurality of programmable digital circuit blocks coupled to the IO port and the first analog circuit block by the programmable interconnect structure.

Assignees

• Cypress Semiconductor Corp

Inventors

• Snyder Warren S
• Mar Monte

Classifications

• H03K19/17736

  Structural details of routing resources · CPC title

• H03K19/173 Primary

  using elementary logic circuits as components · CPC title

• H03K19/1733

  Controllable logic circuits (H03K19/177 takes precedence) · CPC title

• H03K19/17748

  Structural details of configuration resources · CPC title

• H03K19/08 Primary

  using semiconductor devices (H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12) · CPC title