Wide range level shifter for low voltage input applications

Patent metadata

Field	Value
Publication number	US-9843326-B1
Application number	US-201615227979-A
Country	US
Kind code	B1
Filing date	Aug 4, 2016
Priority date	Aug 4, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

Device and a method of configuring a voltage level shifter is disclosed. The device includes a traditional level shifter circuit (TLSC), a first control circuit (FCC) cross-coupled to a second control circuit (SCC). The FCC is coupled to receive an inverse of an input at a first input node and provide a first output at a first output node. The SCC is coupled to receive the input at a second input node and provide a second output at a second output node and the TLSC is configured to provide an output at an output node in response to the first output received at the first output node and the second output received at the second output node. A first power source is configured to provide a first power supply voltage to the TLSC, the FCC and the SCC. The output is latched to track the input. The TLSC, the FCC and the SCC are coupled to a ground reference node.

First claim

What is claimed is:

1. A device comprising:
a level shifter circuit (LSC);
a first control circuit (FCC) cross-coupled to a second control circuit (SCC), wherein the FCC is coupled to receive an inverse of an input at a first input node and provide a first output at a first output node, wherein the SCC is coupled to receive the input at a second input node and provide a second output at a second output node, wherein the LSC is configured to provide an output at an output node in response to the first output received at the first output node and the second output received at the second output node;
a first power source configured to provide a first power supply voltage to the LSC, the FCC and the SCC; and
a second power source configured to provide a second power supply voltage to the FCC and the SCC, wherein the output is latched to track the input, wherein the LSC, the FCC and the SCC are coupled to a ground reference node.

2. The device of claim 1 , wherein the FCC is configured to switch the first output between the first power supply voltage and the ground reference node voltage in response to the inverse of the input switching between the ground reference node voltage and the second power supply voltage.

3. The device of claim 2 , wherein the SCC is configured to switch the second output between the ground reference voltage and the first power supply voltage in response to the input switching between the second power supply voltage and the ground reference node voltage.

4. The device of claim 2 , wherein the output is configured to switch between the first power supply voltage and the ground reference node voltage in response to the input switching between the second power supply voltage and the ground reference node voltage.

5. The device of claim 2 , further comprising:
an inverter circuit powered by the second power source, wherein the inverter circuit is configured to generate the inverse of the input in response to receiving the input.

6. The device of claim 2 , wherein the FCC further comprises:
a third (MN3) n-channel transistor having a gate coupled to receive the inverse of the input at the first input node, wherein an operating state of the MN3 transistor is switched in response to the inverse of the input;
a pair of fifth (MP5) and sixth (MP6) p-channel transistors coupled in series, wherein respective gates of the MP5 and MP6 transistors are coupled to receive the inverse of the input at the first input node, wherein a drain of the MP6 transistor is coupled to a drain of the MN3 transistor to form the first output node;
a third (MP3) p-channel transistor having a gate coupled to receive the second output at the second output node, wherein a source of the MP3 transistor is coupled to the first power source, wherein a drain of the MP3 transistor is coupled to a source of the MP5 transistor; and
a fifth (MN5) n-channel transistor having a gate coupled to receive the input at a third input node, wherein a source of the MN5 transistor is coupled to the first output node, wherein a drain of the MN5 transistor is coupled to the second power source.

7. The device of claim 6 , wherein the second power supply voltage is configured to be at least equal to a threshold voltage of the MN3 transistor, wherein the MN5 transistor is configured to speed up response of the output in response to a change in the input.

8. The device of claim 2 , wherein the SCC further comprises:
a fourth (MN4) n-channel transistor having a gate coupled to receive the input at the second input node, wherein an operating state of the MN4 transistor is switched in response to the input;
a pair of seventh (MP7) and eighth (MP8) p-channel transistors coupled in series, wherein respective gates of the MP7 and MP8 transistors are coupled to receive the input at the second input node, wherein a drain of the MP8 transistor is coupled to a drain of the MN4 transistor to form the second output node;
a fourth (MP4) p-channel transistor having a gate coupled to receive the first output at the first output node, wherein a source of the MP4 transistor is coupled to the first power source, wherein a drain of the MP4 transistor is coupled to a source of the MP7 transistor; and
a sixth (MN6) n-channel transistor having a gate coupled to receive the inverse of the input at the fourth input node, wherein a source of the MN6 transistor is coupled to the second output node, wherein a drain of the MN6 transistor is coupled to the second power source.

9. The device of claim 8 , wherein the second power supply voltage is configured to be at least equal to a threshold voltage of the MN4 transistor, wherein the MN6 transistor is configured to speed up response of the output in response to a change in the input.

10. The device of claim 1 , wherein the LSC comprises:
a pair of cross-coupled first (MP1) and second (MP2) p-channel transistors, wherein a gate of the MP1 transistor is coupled to the output node, wherein a gate of the MP2 transistor is coupled to a drain of the MP1 transistor, wherein a source of the MP1 and MP2 transistors is coupled to the first power source; and
a differential pair of first (MN1) and second (MN2) n-channel transistors, wherein
the MN1 transistor having a gate coupled to receive the first output at the first output node, wherein a source of the MN1 transistor is coupled to the ground reference node, wherein a drain of the MN1 transistor is coupled to a drain of the MP1 transistor, and
the MN2 transistor having a gate coupled to receive the second output at the second output node, wherein a source of the MN2 transistor is coupled to the ground reference node, wherein a drain of the MN2 transistor is coupled to a drain of the MP2 transistor.

11. A device comprising a level shifter circuit (LSC);
a first control circuit (FCC) cross-coupled to a second control circuit (SCC), wherein the FCC is coupled to receive an inverse of an input at a first input node and provide a first output at a first output node, wherein the SCC is coupled to receive the input at a second input node and provide a second output at a second output node, wherein the LSC is configured to provide an output at an output node in response to the first output received at the first output node and the second output received at the second output node;
a first power source configured to provide a first power supply voltage to the LSC, the FCC and the SCC, wherein the output is latched to track the input, wherein the LSC, the FCC and the SCC are coupled to a ground reference node; and
a second power source configured to provide the second power supply voltage to the FCC and the SCC, wherein the FCC is coupled to receive the inverse of the input at the first input node and configured to switch the first output between the first power supply voltage and the ground reference node voltage in response to the inverse of the input switching between the ground reference node voltage and the second power supply voltage, wherein the SCC is configured to receive the input at the second input node.

12. A method comprising:
configuring a first power source to provide a first power supply voltage;
configuring a second power source to provide a second power supply voltage, wherein the second power source provides a lower power supply voltage compared to the first power source;
configuring a first control circuit (FCC) to shift a voltage level of an inverse of an input operating between the second power supply voltage and a ground reference to a first output operating between the first power supply voltage and the ground reference, wherein the FCC comprises
a third (MN3) n-channel transistor having a gate coupled to receive the inv

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Xu Fei
• Auyeung On
• Chen Qi
• Luo Zhihong
• Lau Sui Chor Benjamin
• Nguyen Bai Yen

Classifications

• H03K19/0948 Primary

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title